42 lines
1.6 KiB
Plaintext
42 lines
1.6 KiB
Plaintext
# Run VPR for the s298 design
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vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/s298.blif --write_rr_graph example_rr_graph.xml
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
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# Write out the architecture XML as a proof
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#write_openfpga_arch -f ./arch_echo.xml
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# Annotate the OpenFPGA architecture to VPR data base
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link_openfpga_arch #--verbose
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# Check and correct any naming conflicts in the BLIF netlist
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check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
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# Apply fix-up to clustering nets based on routing results
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pb_pin_fixup --verbose
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# Apply fix-up to Look-Up Table truth tables based on packing results
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lut_truth_table_fixup #--verbose
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# Build the module graph
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# - Enabled compression on routing architecture modules
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# - Enable pin duplication on grid modules
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build_fabric --compress_routing --duplicate_grid_pin #--verbose
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# Repack the netlist to physical pbs
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# This must be done before bitstream generator and testbench generation
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# Strongly recommend it is done after all the fix-up have been applied
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repack --verbose
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# Build the bitstream
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# - Output the fabric-independent bitstream to a file
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fpga_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
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# Write the Verilog netlit for FPGA fabric
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# - Enable the use of explicit port mapping in Verilog netlist
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write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
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# Finish and exit OpenFPGA
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exit
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