115 lines
5.5 KiB
C++
115 lines
5.5 KiB
C++
#ifndef OPENFPGA_CONTEXT_H
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#define OPENFPGA_CONTEXT_H
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#include <vector>
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#include "vpr_context.h"
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#include "openfpga_arch.h"
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#include "vpr_netlist_annotation.h"
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#include "vpr_device_annotation.h"
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#include "vpr_clustering_annotation.h"
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#include "vpr_placement_annotation.h"
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#include "vpr_routing_annotation.h"
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#include "mux_library.h"
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#include "tile_direct.h"
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#include "module_manager.h"
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#include "openfpga_flow_manager.h"
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#include "bitstream_manager.h"
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#include "device_rr_gsb.h"
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/********************************************************************
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* This file includes the declaration of the date structure
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* OpenfpgaContext, which is used for data exchange between
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* different modules in OpenFPGA shell environment
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*
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* If a command of OpenFPGA needs to exchange data with other commands,
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* it must use this data structure to access/mutate.
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* In such case, you must add data structures to OpenfpgaContext
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*
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* Note:
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* Please respect to the following rules when using the OpenfpgaContext
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* 1. This data structure will be created only once in the main() function
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* The data structure is design to be large and contain all the
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* data structure required by each module of OpenFPGA core engine.
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* Do NOT create or duplicate in your own module!
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* 2. Be clear in your mind if you want to access/mutate the data inside OpenfpgaContext
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* Read-only data should be accessed by
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* const OpenfpgaContext&
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* Mutate should use reference
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* OpenfpgaContext&
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* 3. Please keep the definition of OpenfpgaContext short
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* Do put ONLY well-modularized data structure under this root.
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* 4. We build this data structure based on the Context from VPR
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* which does NOT allow users to copy the internal members
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* This is due to that the data structures in the OpenFPGA context
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* are typically big in terms of memory
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*******************************************************************/
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class OpenfpgaContext : public Context {
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public: /* Public accessors */
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const openfpga::Arch& arch() const { return arch_; }
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const openfpga::VprDeviceAnnotation& vpr_device_annotation() const { return vpr_device_annotation_; }
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const openfpga::VprNetlistAnnotation& vpr_netlist_annotation() const { return vpr_netlist_annotation_; }
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const openfpga::VprClusteringAnnotation& vpr_clustering_annotation() const { return vpr_clustering_annotation_; }
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const openfpga::VprPlacementAnnotation& vpr_placement_annotation() const { return vpr_placement_annotation_; }
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const openfpga::VprRoutingAnnotation& vpr_routing_annotation() const { return vpr_routing_annotation_; }
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const openfpga::DeviceRRGSB& device_rr_gsb() const { return device_rr_gsb_; }
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const openfpga::MuxLibrary& mux_lib() const { return mux_lib_; }
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const openfpga::TileDirect& tile_direct() const { return tile_direct_; }
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const openfpga::ModuleManager& module_graph() const { return module_graph_; }
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const openfpga::FlowManager& flow_manager() const { return flow_manager_; }
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const openfpga::BitstreamManager& bitstream_manager() const { return bitstream_manager_; }
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const std::vector<openfpga::ConfigBitId>& fabric_bitstream() const { return fabric_bitstream_; }
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public: /* Public mutators */
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openfpga::Arch& mutable_arch() { return arch_; }
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openfpga::VprDeviceAnnotation& mutable_vpr_device_annotation() { return vpr_device_annotation_; }
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openfpga::VprNetlistAnnotation& mutable_vpr_netlist_annotation() { return vpr_netlist_annotation_; }
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openfpga::VprClusteringAnnotation& mutable_vpr_clustering_annotation() { return vpr_clustering_annotation_; }
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openfpga::VprPlacementAnnotation& mutable_vpr_placement_annotation() { return vpr_placement_annotation_; }
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openfpga::VprRoutingAnnotation& mutable_vpr_routing_annotation() { return vpr_routing_annotation_; }
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openfpga::DeviceRRGSB& mutable_device_rr_gsb() { return device_rr_gsb_; }
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openfpga::MuxLibrary& mutable_mux_lib() { return mux_lib_; }
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openfpga::TileDirect& mutable_tile_direct() { return tile_direct_; }
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openfpga::ModuleManager& mutable_module_graph() { return module_graph_; }
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openfpga::FlowManager& mutable_flow_manager() { return flow_manager_; }
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openfpga::BitstreamManager& mutable_bitstream_manager() { return bitstream_manager_; }
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std::vector<openfpga::ConfigBitId>& mutable_fabric_bitstream() { return fabric_bitstream_; }
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private: /* Internal data */
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/* Data structure to store information from read_openfpga_arch library */
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openfpga::Arch arch_;
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/* Annotation to pb_type of VPR */
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openfpga::VprDeviceAnnotation vpr_device_annotation_;
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/* Naming fix to netlist */
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openfpga::VprNetlistAnnotation vpr_netlist_annotation_;
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/* Pin net fix to cluster results */
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openfpga::VprClusteringAnnotation vpr_clustering_annotation_;
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/* Placement results */
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openfpga::VprPlacementAnnotation vpr_placement_annotation_;
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/* Routing results annotation */
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openfpga::VprRoutingAnnotation vpr_routing_annotation_;
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/* Device-level annotation */
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openfpga::DeviceRRGSB device_rr_gsb_;
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/* Library of physical implmentation of routing multiplexers */
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openfpga::MuxLibrary mux_lib_;
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/* Inner/inter-column/row tile direct connections */
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openfpga::TileDirect tile_direct_;
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/* Fabric module graph */
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openfpga::ModuleManager module_graph_;
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/* Bitstream database */
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openfpga::BitstreamManager bitstream_manager_;
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std::vector<openfpga::ConfigBitId> fabric_bitstream_;
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/* Flow status */
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openfpga::FlowManager flow_manager_;
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};
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#endif
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