AurelienAlacchi 3f5cc59c0a Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200) ... * Add required files for LUTRAM integration and testing * Add task for lutram * Repair format (tab and space mismatched) * Add disclaimer in architecture file Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>		2021-01-29 10:19:05 -07:00
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arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200)	2021-01-29 10:19:05 -07:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	Bumping yosys submodule with the latest changes done in yosys repo related to OpenFPGA flow	2021-01-08 07:08:24 -08:00
openfpga_arch	Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200)	2021-01-29 10:19:05 -07:00
openfpga_cell_library	Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200)	2021-01-29 10:19:05 -07:00
openfpga_shell_scripts	[Script] Use pin constraints in template script	2021-01-19 17:42:25 -07:00
openfpga_simulation_settings	[Flow] Update simulation settings for multiple clock to allow unique clock port name	2021-01-15 10:35:43 -07:00
scripts	[Regression] Upgraded runtime enviroment to python3.8	2021-01-26 16:40:45 -07:00
tasks	Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200)	2021-01-29 10:19:05 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200)	2021-01-29 10:19:05 -07:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00