27 lines
1003 B
Plaintext
27 lines
1003 B
Plaintext
**************************************************************************************************
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* Example VTR experiments complete with scripts, benchmarks, architectures, and expected results
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**************************************************************************************************
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Starting out:
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basic_flow - Run the whole VTR flow to map a simple Verilog circuit to an FPGA architecture
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Advanced (Flagshp experiment):
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timing - Run the flagship VTR benchmarks on our comprehensive, realistic architecture file
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timing_chain - Same as above but this time with carry chains
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Legacy:
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regression_mcnc - Run VTR on the historical MCNC benchmarks on a legacy architecture file
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(Note: This is only useful for comparing to the past, it is not realistic in the modern world)
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Custom, unique logic blocks:
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regression_titan\titan_small - Simplified Altera Stratix IV (commercial FPGA) architecture capture
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regression_fpu_hard_block_arch - Custom hard FPU logic block architecture
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