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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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3e07d7d5e0
OpenFPGA
/
openfpga
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tangxifan
3e07d7d5e0
finish net addition to LbRouter. Found a bug in pb pin fix-up. Need to consider clustered I/O block z offset
2020-02-20 20:26:20 -07:00
..
src
finish net addition to LbRouter. Found a bug in pb pin fix-up. Need to consider clustered I/O block z offset
2020-02-20 20:26:20 -07:00
test_blif
use a micro benchmark for vpr quick-run
2020-01-26 17:56:22 -07:00
test_openfpga_arch
add lut module builder
2020-02-12 19:52:41 -07:00
test_script
finish net addition to LbRouter. Found a bug in pb pin fix-up. Need to consider clustered I/O block z offset
2020-02-20 20:26:20 -07:00
test_vpr_arch
add rr_segment binding to circuit model
2020-02-12 11:21:40 -07:00
CMakeLists.txt
start implement openfpga shell and use vpr as a macro
2020-01-22 20:20:10 -07:00