130 lines
5.0 KiB
ReStructuredText
130 lines
5.0 KiB
ReStructuredText
.. _direct_interconnect:
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Inter-Tile Direct Interconnection extensions
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--------------------------------------------
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This section introduces extensions on the architecture description file about existing interconnection description.
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Directlist
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~~~~~~~~~~
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The original direct connections in the directlist section are documented here_. Its description is given below:
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.. _here: http://docs.verilogtorouting.org/en/latest/arch/reference/?highlight=directlist#direct-inter-block-connections
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.. code-block:: xml
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<directlist>
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<direct name="string" from_pin="string" to_pin="string" x_offset="int" y_offset="int" z_offset="int" switch_name="string"/>
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</directlist>
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.. note:: These options are required
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In the OpenFPGA architecture file, you may define additional attributes for each VPR's direct connection:
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.. code-block:: xml
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<direct_connection>
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<direct name="string" circuit_model_name="string" interconnection_type="string" x_dir="string" y_dir="string"/>
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</directlist>
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.. note:: these options are optional. However, if ``interconnection_type`` is set to ``inter_column`` or ``inter_row, then `x_dir` and `y_dir` are required.
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.. option:: interconnection_type="<string>"
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Available types are ``inner_column_or_row`` | ``part_of_cb`` | ``inter_column`` | ``inter_row``
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- ``inner_column_or_row`` indicates the direct connections are between tiles in the same column or row. This is the default value.
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- ``part_of_cb`` indicates the direct connections will drive routing multiplexers in connection blocks. Therefore, it is no longer a strict point-to-point direct connection.
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- ``inter_column`` indicates the direct connections are between tiles in two columns
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- ``inter_row`` indicates the direct connections are between tiles in two rows
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The type ``part_of_cb`` is required, when VPR architecture defines feedback connections like:
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.. code-block:: xml
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<directlist>
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<direct name="feedback" from_pin="clb.O" to_pin="clb.I" x_offset="0" y_offset="0" z_offset="0"/>
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</directlist>
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.. note:: The following syntax is only applicable to ``inter_column`` and ``inter_row``
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.. option:: x_dir="<string>"
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Available directionalities are ``positive`` | ``negative``, specifies if the next cell to connect has a bigger or lower ``x`` value.
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Considering a coordinate system where (0,0) is the origin at the bottom left and ``x`` and ``y`` are positives:
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- x_dir="positive":
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- interconnection_type="column": a column will be connected to a column on the ``right``, if it exists.
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- interconnection_type="row": the most on the ``right`` cell from a row connection will connect the most on the ``left`` cell of next row, if it exists.
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- x_dir="negative":
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- interconnection_type="column": a column will be connected to a column on the ``left``, if it exists.
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- interconnection_type="row": the most on the ``left`` cell from a row connection will connect the most on the ``right`` cell of next row, if it exists.
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.. option:: y_dir="<string>"
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Available directionalities are ``positive`` | ``negative``, specifies if the next cell to connect has a bigger or lower x value.
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Considering a coordinate system where (0,0) is the origin at the bottom left and `x` and `y` are positives:
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- y_dir="positive":
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- interconnection_type="column": the ``bottom`` cell of a column will be connected to the next column ``top`` cell, if it exists.
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- interconnection_type="row": a row will be connected on an ``above`` row, if it exists.
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- y_dir="negative":
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- interconnection_type="column": the ``top`` cell of a column will be connected to the next column ``bottom`` cell, if it exists.
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- interconnection_type="row": a row will be connected on a row ``below``, if it exists.
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Example
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~~~~~~~
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For this example, we will study a scan-chain implementation. The description could be:
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In VPR architecture:
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.. code-block:: xml
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<directlist>
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<direct name="scff_chain" from_pin="clb.sc_out" to_pin="clb.sc_in" x_offset="0" y_offset="-1" z_offset="0"/>
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</directlist>
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In OpenFPGA architecture:
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.. code-block:: xml
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<direct_connection>
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<direct name="scff_chain" interconnection_type="column" x_dir="positive" y_dir="positive"/>
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</direct_connection>
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:numref:`fig_p2p_exple` is the graphical representation of the above scan-chain description on a 4x4 FPGA.
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.. _fig_p2p_exple:
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.. figure:: ./figures/point2point_example.png
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An example of scan-chain implementation
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In this figure, the red arrows represent the initial direct connection. The green arrows represent the point to point connection to connect all the columns of CLB.
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Truth table
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~~~~~~~~~~~
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A point to point connection can be applied in different ways than showed in the example section. To help the designer implement his point to point connection, a truth table with our new parameters id provided below.
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:numref:`fig_p2p_trtable` provides all possible variable combination and the connection it will generate.
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.. _fig_p2p_trtable:
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.. figure:: ./figures/point2point_truthtable.png
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Point to point truth table
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