29 lines
1.6 KiB
Bash
29 lines
1.6 KiB
Bash
#!/bin/bash
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# Example of how to run vpr
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# Set variables
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# For FPGA-Verilog ONLY
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benchmark="test_modes"
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OpenFPGA_path="OPENFPGAPATHKEYWORD"
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verilog_output_dirname="${benchmark}_Verilog"
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verilog_output_dirpath="$PWD"
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tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml"
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# VPR critical inputs
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arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml"
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blif_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif"
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act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act "
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verilog_reference="${OpenFPGA_path}/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v"
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vpr_route_chan_width="200"
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# Step A: Make sure a clean start
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# Recompile if needed
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#make clean
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#make -j32
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# Remove previous designs
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rm -rf $verilog_output_dirpath/$verilog_output_dirname
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# Run VPR
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#valgrind
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./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis #--fpga_x2p_compact_routing_hierarchy
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