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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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3a0d3b4e95
OpenFPGA
/
openfpga
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tangxifan
ece651ade2
bug fixed in the configuration chian errrors
2020-06-11 19:31:10 -06:00
..
src
bug fixed in the configuration chian errrors
2020-06-11 19:31:10 -06:00
test_blif
add missing files for micro benchmarks
2020-03-20 11:08:55 -06:00
test_openfpga_arch
now inout must be global port and I/O port so that it will appear in the top-level module
2020-04-08 16:54:08 -06:00
test_script
bug fix in pnr sdc grid writer for module paths in hierarchical view
2020-06-11 19:31:05 -06:00
test_vpr_arch
add arch file with spy pads
2020-04-22 12:56:09 -06:00
CMakeLists.txt
add simulation ini file writer
2020-02-27 18:01:47 -07:00