1447 lines
29 KiB
Plaintext
1447 lines
29 KiB
Plaintext
# Benchmark "sasc" written by ABC on Mon Aug 29 15:33:11 2005
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.model sasc
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.inputs clk rst rxd_i cts_i sio_ce sio_ce_x4 re_i we_i din_i[0] din_i[1] \
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din_i[2] din_i[3] din_i[4] din_i[5] din_i[6] din_i[7]
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.outputs txd_o rts_o full_o empty_o dout_o[0] dout_o[1] dout_o[2] dout_o[3] \
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dout_o[4] dout_o[5] dout_o[6] dout_o[7]
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.latch rx_fifo_gb_reg_in rx_fifo_gb_reg 2
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.latch \rx_fifo_wp_reg[0]_in \rx_fifo_wp_reg[0] 0
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.latch \rx_fifo_mem_reg[1][6]_in \rx_fifo_mem_reg[1][6] 2
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.latch \rx_fifo_mem_reg[1][7]_in \rx_fifo_mem_reg[1][7] 2
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.latch \rx_fifo_mem_reg[2][0]_in \rx_fifo_mem_reg[2][0] 2
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.latch \rx_fifo_mem_reg[2][1]_in \rx_fifo_mem_reg[2][1] 2
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.latch \rx_fifo_mem_reg[2][2]_in \rx_fifo_mem_reg[2][2] 2
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.latch \rx_fifo_mem_reg[2][3]_in \rx_fifo_mem_reg[2][3] 2
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.latch \rx_fifo_mem_reg[2][4]_in \rx_fifo_mem_reg[2][4] 2
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.latch \rx_fifo_mem_reg[2][5]_in \rx_fifo_mem_reg[2][5] 2
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.latch \rx_fifo_mem_reg[2][6]_in \rx_fifo_mem_reg[2][6] 2
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.latch \rx_fifo_mem_reg[2][7]_in \rx_fifo_mem_reg[2][7] 2
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.latch \rx_fifo_mem_reg[1][0]_in \rx_fifo_mem_reg[1][0] 2
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.latch \rx_fifo_mem_reg[1][1]_in \rx_fifo_mem_reg[1][1] 2
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.latch \rx_fifo_mem_reg[1][2]_in \rx_fifo_mem_reg[1][2] 2
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.latch \rx_fifo_mem_reg[1][3]_in \rx_fifo_mem_reg[1][3] 2
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.latch \rx_fifo_mem_reg[1][4]_in \rx_fifo_mem_reg[1][4] 2
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.latch \rx_fifo_mem_reg[1][5]_in \rx_fifo_mem_reg[1][5] 2
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.latch \rx_fifo_mem_reg[3][0]_in \rx_fifo_mem_reg[3][0] 2
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.latch \rx_fifo_mem_reg[3][1]_in \rx_fifo_mem_reg[3][1] 2
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.latch \rx_fifo_mem_reg[3][2]_in \rx_fifo_mem_reg[3][2] 2
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.latch \rx_fifo_mem_reg[3][3]_in \rx_fifo_mem_reg[3][3] 2
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.latch \rx_fifo_mem_reg[3][4]_in \rx_fifo_mem_reg[3][4] 2
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.latch \rx_fifo_mem_reg[3][5]_in \rx_fifo_mem_reg[3][5] 2
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.latch \rx_fifo_mem_reg[3][6]_in \rx_fifo_mem_reg[3][6] 2
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.latch \rx_fifo_mem_reg[3][7]_in \rx_fifo_mem_reg[3][7] 2
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.latch \rx_fifo_mem_reg[0][0]_in \rx_fifo_mem_reg[0][0] 2
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.latch \rx_fifo_mem_reg[0][1]_in \rx_fifo_mem_reg[0][1] 2
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.latch \rx_fifo_mem_reg[0][2]_in \rx_fifo_mem_reg[0][2] 2
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.latch \rx_fifo_mem_reg[0][3]_in \rx_fifo_mem_reg[0][3] 2
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.latch \rx_fifo_mem_reg[0][4]_in \rx_fifo_mem_reg[0][4] 2
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.latch \rx_fifo_mem_reg[0][5]_in \rx_fifo_mem_reg[0][5] 2
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.latch \rx_fifo_mem_reg[0][6]_in \rx_fifo_mem_reg[0][6] 2
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.latch \rx_fifo_mem_reg[0][7]_in \rx_fifo_mem_reg[0][7] 2
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.latch \rx_bit_cnt_reg[1]_in \rx_bit_cnt_reg[1] 2
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.latch \rx_fifo_wp_reg[1]_in \rx_fifo_wp_reg[1] 0
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.latch \rx_bit_cnt_reg[3]_in \rx_bit_cnt_reg[3] 2
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.latch \rx_bit_cnt_reg[0]_in \rx_bit_cnt_reg[0] 2
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.latch \rx_bit_cnt_reg[2]_in \rx_bit_cnt_reg[2] 2
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.latch \rxr_reg[3]_in \rxr_reg[3] 2
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.latch \rxr_reg[9]_in \rxr_reg[9] 2
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.latch \rxr_reg[2]_in \rxr_reg[2] 2
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.latch \rxr_reg[4]_in \rxr_reg[4] 2
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.latch \rxr_reg[5]_in \rxr_reg[5] 2
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.latch \rxr_reg[6]_in \rxr_reg[6] 2
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.latch \rxr_reg[8]_in \rxr_reg[8] 2
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.latch \rxr_reg[7]_in \rxr_reg[7] 2
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.latch \tx_bit_cnt_reg[3]_in \tx_bit_cnt_reg[3] 2
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.latch tx_fifo_gb_reg_in tx_fifo_gb_reg 2
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.latch \hold_reg_reg[6]_in \hold_reg_reg[6] 2
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.latch \hold_reg_reg[7]_in \hold_reg_reg[7] 2
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.latch \hold_reg_reg[8]_in \hold_reg_reg[8] 2
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.latch \hold_reg_reg[1]_in \hold_reg_reg[1] 2
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.latch \hold_reg_reg[2]_in \hold_reg_reg[2] 2
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.latch \hold_reg_reg[3]_in \hold_reg_reg[3] 2
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.latch \hold_reg_reg[4]_in \hold_reg_reg[4] 2
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.latch \tx_bit_cnt_reg[2]_in \tx_bit_cnt_reg[2] 2
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.latch \hold_reg_reg[5]_in \hold_reg_reg[5] 2
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.latch txf_empty_r_reg_in txf_empty_r_reg 2
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.latch \tx_fifo_mem_reg[2][1]_in \tx_fifo_mem_reg[2][1] 2
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.latch \dpll_state_reg[0]_in \dpll_state_reg[0] 1
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.latch rts_o_reg_in rts_o_reg 2
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.latch \tx_bit_cnt_reg[0]_in \tx_bit_cnt_reg[0] 2
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.latch \tx_fifo_mem_reg[1][0]_in \tx_fifo_mem_reg[1][0] 2
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.latch \tx_fifo_mem_reg[1][1]_in \tx_fifo_mem_reg[1][1] 2
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.latch \tx_fifo_mem_reg[1][2]_in \tx_fifo_mem_reg[1][2] 2
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.latch \tx_fifo_mem_reg[1][3]_in \tx_fifo_mem_reg[1][3] 2
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.latch \tx_fifo_mem_reg[1][4]_in \tx_fifo_mem_reg[1][4] 2
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.latch \tx_fifo_mem_reg[1][6]_in \tx_fifo_mem_reg[1][6] 2
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.latch \tx_fifo_mem_reg[1][7]_in \tx_fifo_mem_reg[1][7] 2
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.latch \tx_fifo_mem_reg[2][0]_in \tx_fifo_mem_reg[2][0] 2
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.latch \tx_fifo_mem_reg[2][2]_in \tx_fifo_mem_reg[2][2] 2
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.latch \tx_fifo_mem_reg[2][3]_in \tx_fifo_mem_reg[2][3] 2
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.latch \tx_fifo_mem_reg[2][4]_in \tx_fifo_mem_reg[2][4] 2
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.latch \tx_fifo_mem_reg[2][6]_in \tx_fifo_mem_reg[2][6] 2
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.latch \tx_fifo_mem_reg[2][7]_in \tx_fifo_mem_reg[2][7] 2
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.latch txd_o_reg_in txd_o_reg 2
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.latch \tx_fifo_rp_reg[1]_in \tx_fifo_rp_reg[1] 0
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.latch \hold_reg_reg[0]_in \hold_reg_reg[0] 2
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.latch \tx_fifo_mem_reg[1][5]_in \tx_fifo_mem_reg[1][5] 2
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.latch \tx_fifo_mem_reg[2][5]_in \tx_fifo_mem_reg[2][5] 2
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.latch \tx_fifo_mem_reg[3][1]_in \tx_fifo_mem_reg[3][1] 2
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.latch \tx_fifo_mem_reg[3][6]_in \tx_fifo_mem_reg[3][6] 2
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.latch rx_valid_r_reg_in rx_valid_r_reg 2
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.latch \tx_fifo_mem_reg[3][5]_in \tx_fifo_mem_reg[3][5] 2
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.latch change_reg_in change_reg 2
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.latch \tx_fifo_mem_reg[0][0]_in \tx_fifo_mem_reg[0][0] 2
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.latch \tx_fifo_mem_reg[0][3]_in \tx_fifo_mem_reg[0][3] 2
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.latch \tx_fifo_mem_reg[0][4]_in \tx_fifo_mem_reg[0][4] 2
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.latch \tx_fifo_mem_reg[0][7]_in \tx_fifo_mem_reg[0][7] 2
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.latch \tx_fifo_mem_reg[0][2]_in \tx_fifo_mem_reg[0][2] 2
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.latch \tx_fifo_mem_reg[3][0]_in \tx_fifo_mem_reg[3][0] 2
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.latch \tx_fifo_mem_reg[3][2]_in \tx_fifo_mem_reg[3][2] 2
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.latch \tx_fifo_mem_reg[3][3]_in \tx_fifo_mem_reg[3][3] 2
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.latch \tx_fifo_mem_reg[3][4]_in \tx_fifo_mem_reg[3][4] 2
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.latch \tx_fifo_mem_reg[3][7]_in \tx_fifo_mem_reg[3][7] 2
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.latch \rx_fifo_rp_reg[1]_in \rx_fifo_rp_reg[1] 0
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.latch \hold_reg_reg[9]_in \hold_reg_reg[9] 2
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.latch \tx_fifo_mem_reg[0][6]_in \tx_fifo_mem_reg[0][6] 2
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.latch \tx_fifo_mem_reg[0][5]_in \tx_fifo_mem_reg[0][5] 2
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.latch \tx_fifo_mem_reg[0][1]_in \tx_fifo_mem_reg[0][1] 2
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.latch \tx_bit_cnt_reg[1]_in \tx_bit_cnt_reg[1] 2
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.latch rx_sio_ce_reg_in rx_sio_ce_reg 2
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.latch shift_en_r_reg_in shift_en_r_reg 2
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.latch \tx_fifo_wp_reg[1]_in \tx_fifo_wp_reg[1] 0
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.latch \dpll_state_reg[1]_in \dpll_state_reg[1] 0
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.latch rx_valid_reg_in rx_valid_reg 2
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.latch \rx_fifo_rp_reg[0]_in \rx_fifo_rp_reg[0] 0
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.latch rx_go_reg_in rx_go_reg 2
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.latch \tx_fifo_rp_reg[0]_in \tx_fifo_rp_reg[0] 0
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.latch load_reg_in load_reg 2
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.latch rx_sio_ce_r2_reg_in rx_sio_ce_r2_reg 2
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.latch \tx_fifo_wp_reg[0]_in \tx_fifo_wp_reg[0] 0
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.latch shift_en_reg_in shift_en_reg 2
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.latch rx_sio_ce_r1_reg_in rx_sio_ce_r1_reg 2
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.latch rxd_r_reg_in rxd_r_reg 2
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.latch rxd_s_reg_in rxd_s_reg 2
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.names [145]
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0
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.names [146]
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1
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.names rx_fifo_gb_reg [147]
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1 1
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.names \rx_fifo_wp_reg[0] [148]
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1 1
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.names \rx_fifo_mem_reg[1][6] [149]
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1 1
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.names \rx_fifo_mem_reg[1][7] [150]
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1 1
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.names \rx_fifo_mem_reg[2][0] [151]
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1 1
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.names \rx_fifo_mem_reg[2][1] [152]
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1 1
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.names \rx_fifo_mem_reg[2][2] [153]
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1 1
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.names \rx_fifo_mem_reg[2][3] [154]
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1 1
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.names \rx_fifo_mem_reg[2][4] [155]
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1 1
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.names \rx_fifo_mem_reg[2][5] [156]
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1 1
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.names \rx_fifo_mem_reg[2][6] [157]
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1 1
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.names \rx_fifo_mem_reg[2][7] [158]
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1 1
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.names \rx_fifo_mem_reg[1][0] [159]
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1 1
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.names \rx_fifo_mem_reg[1][1] [160]
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1 1
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.names \rx_fifo_mem_reg[1][2] [161]
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1 1
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.names \rx_fifo_mem_reg[1][3] [162]
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1 1
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.names \rx_fifo_mem_reg[1][4] [163]
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1 1
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.names \rx_fifo_mem_reg[1][5] [164]
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1 1
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.names \rx_fifo_mem_reg[3][0] [165]
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1 1
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.names \rx_fifo_mem_reg[3][1] [166]
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1 1
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.names \rx_fifo_mem_reg[3][2] [167]
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1 1
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.names \rx_fifo_mem_reg[3][3] [168]
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1 1
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.names \rx_fifo_mem_reg[3][4] [169]
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1 1
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.names \rx_fifo_mem_reg[3][5] [170]
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1 1
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.names \rx_fifo_mem_reg[3][6] [171]
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1 1
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.names \rx_fifo_mem_reg[3][7] [172]
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1 1
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.names \rx_fifo_mem_reg[0][0] [173]
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1 1
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.names \rx_fifo_mem_reg[0][1] [174]
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1 1
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.names \rx_fifo_mem_reg[0][2] [175]
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1 1
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.names \rx_fifo_mem_reg[0][3] [176]
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1 1
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.names \rx_fifo_mem_reg[0][4] [177]
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1 1
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.names \rx_fifo_mem_reg[0][5] [178]
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1 1
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.names \rx_fifo_mem_reg[0][6] [179]
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1 1
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.names \rx_fifo_mem_reg[0][7] [180]
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1 1
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.names [230] [607] [648] rx_fifo_gb_reg_in
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11- 0
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--1 0
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.names \rx_bit_cnt_reg[1] [182]
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1 1
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.names \rx_fifo_wp_reg[1] [183]
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1 1
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.names \rx_bit_cnt_reg[3] [184]
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1 1
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.names [672] [625] [232] \rx_fifo_wp_reg[0]_in
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00- 1
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--0 1
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.names [414] [150] [242] \rx_fifo_mem_reg[1][7]_in
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01- 1
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1-1 1
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.names [352] [151] [242] \rx_fifo_mem_reg[2][0]_in
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01- 1
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1-1 1
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.names [353] [152] [245] \rx_fifo_mem_reg[2][1]_in
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01- 1
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1-1 1
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.names [413] [149] [244] \rx_fifo_mem_reg[1][6]_in
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01- 1
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1-1 1
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.names \rx_bit_cnt_reg[0] [190]
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1 1
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.names \rx_bit_cnt_reg[2] [191]
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1 1
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.names [355] [154] [243] \rx_fifo_mem_reg[2][3]_in
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01- 1
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1-1 1
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.names [354] [153] [245] \rx_fifo_mem_reg[2][2]_in
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01- 1
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1-1 1
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.names [356] [155] [242] \rx_fifo_mem_reg[2][4]_in
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01- 1
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1-1 1
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.names [357] [156] [243] \rx_fifo_mem_reg[2][5]_in
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01- 1
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1-1 1
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.names [358] [157] [245] \rx_fifo_mem_reg[2][6]_in
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01- 1
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1-1 1
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.names [359] [158] [244] \rx_fifo_mem_reg[2][7]_in
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01- 1
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1-1 1
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.names [417] [160] [242] \rx_fifo_mem_reg[1][1]_in
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01- 1
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1-1 1
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.names [415] [159] [245] \rx_fifo_mem_reg[1][0]_in
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01- 1
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|
1-1 1
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.names [416] [161] [242] \rx_fifo_mem_reg[1][2]_in
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|
01- 1
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1-1 1
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.names [418] [162] [243] \rx_fifo_mem_reg[1][3]_in
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|
01- 1
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1-1 1
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|
.names [419] [163] [242] \rx_fifo_mem_reg[1][4]_in
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01- 1
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1-1 1
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|
.names [420] [164] [244] \rx_fifo_mem_reg[1][5]_in
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|
01- 1
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1-1 1
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|
.names [360] [165] [244] \rx_fifo_mem_reg[3][0]_in
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|
01- 1
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1-1 1
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.names [361] [166] [245] \rx_fifo_mem_reg[3][1]_in
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|
01- 1
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1-1 1
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|
.names [362] [167] [243] \rx_fifo_mem_reg[3][2]_in
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|
01- 1
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|
1-1 1
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|
.names [363] [168] [244] \rx_fifo_mem_reg[3][3]_in
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|
01- 1
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|
1-1 1
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|
.names [364] [169] [244] \rx_fifo_mem_reg[3][4]_in
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|
01- 1
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|
1-1 1
|
|
.names [366] [170] [243] \rx_fifo_mem_reg[3][5]_in
|
|
01- 1
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|
1-1 1
|
|
.names [367] [171] [245] \rx_fifo_mem_reg[3][6]_in
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|
01- 1
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|
1-1 1
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|
.names [368] [172] [245] \rx_fifo_mem_reg[3][7]_in
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|
01- 1
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|
1-1 1
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|
.names [373] [173] [244] \rx_fifo_mem_reg[0][0]_in
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|
01- 1
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|
1-1 1
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|
.names [369] [174] [243] \rx_fifo_mem_reg[0][1]_in
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|
01- 1
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1-1 1
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.names [374] [175] [245] \rx_fifo_mem_reg[0][2]_in
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01- 1
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1-1 1
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.names [375] [176] [244] \rx_fifo_mem_reg[0][3]_in
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01- 1
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1-1 1
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|
.names [378] [177] [242] \rx_fifo_mem_reg[0][4]_in
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|
01- 1
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|
1-1 1
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|
.names [376] [178] [242] \rx_fifo_mem_reg[0][5]_in
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|
01- 1
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|
1-1 1
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|
.names [372] [179] [243] \rx_fifo_mem_reg[0][6]_in
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|
01- 1
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|
1-1 1
|
|
.names [377] [180] [243] \rx_fifo_mem_reg[0][7]_in
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|
01- 1
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1-1 1
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|
.names \rxr_reg[3] [220]
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1 1
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.names \rxr_reg[9] [221]
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1 1
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.names \rxr_reg[2] [222]
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1 1
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|
.names \rxr_reg[4] [223]
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1 1
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|
.names \rxr_reg[5] [224]
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1 1
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|
.names \rxr_reg[6] [225]
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1 1
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|
.names \rxr_reg[8] [226]
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1 1
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|
.names \rxr_reg[7] [227]
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1 1
|
|
.names [543] [246] rst \rx_bit_cnt_reg[1]_in
|
|
00- 1
|
|
--0 1
|
|
.names [251] [543] rst \rx_bit_cnt_reg[3]_in
|
|
00- 1
|
|
--0 1
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.names [322] [247] [500] [230]
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111 0
|
|
.names [253] [467] \rx_bit_cnt_reg[0]_in
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00 1
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11 0
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.names [252] [467] \rx_bit_cnt_reg[2]_in
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00 1
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01- 1
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1-1 1
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01- 1
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1-1 1
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01- 1
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1-1 1
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01- 1
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1-1 1
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.names [225] [224] [280] \rxr_reg[5]_in
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01- 1
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1-1 1
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|
.names [227] [225] [280] \rxr_reg[6]_in
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01- 1
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1-1 1
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.names [226] [227] [280] \rxr_reg[7]_in
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01- 1
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1-1 1
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.names [221] [226] [280] \rxr_reg[8]_in
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01- 1
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1-1 1
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.names [247] [242]
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0 1
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.names [248] [243]
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0 1
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.names [249] [244]
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0 1
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.names [250] [245]
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0 1
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.names [575] [270] [182] [280] [246]
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11-- 0
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--11 0
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.names [673] [247]
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0 1
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.names [673] [248]
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0 1
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.names [673] [249]
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0 1
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.names [673] [250]
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0 1
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.names [184] [280] [267] [251]
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11- 0
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.names [191] [280] [263] [252]
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11- 0
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.names [629] [280] [262] [253]
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11- 0
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|
--1 0
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.names \tx_bit_cnt_reg[3] [254]
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1 1
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|
.names tx_fifo_gb_reg [255]
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0 1
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0 1
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.names \hold_reg_reg[7] [257]
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0 1
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.names \hold_reg_reg[8] [258]
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0 1
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.names \hold_reg_reg[1] [259]
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0 1
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0 1
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.names \hold_reg_reg[3] [261]
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0 1
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.names [629] [280] [262]
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00 1
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.names [501] [280] [263]
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00 1
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.names \hold_reg_reg[4] [264]
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0 1
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.names \tx_bit_cnt_reg[2] [265]
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1 1
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0 1
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00 1
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0 1
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.names [329] [598] rst \tx_bit_cnt_reg[3]_in
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00- 1
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--0 1
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0 1
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00 1
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01- 1
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1-1 1
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01- 1
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1-1 1
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01- 1
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1-1 1
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.names [516] [385] [598] \hold_reg_reg[8]_in
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01- 1
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1-1 1
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01- 1
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1-1 1
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|
.names [517] [387] [632] \hold_reg_reg[2]_in
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|
01- 1
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|
1-1 1
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|
.names [515] [388] [632] \hold_reg_reg[3]_in
|
|
01- 1
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|
1-1 1
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|
.names [533] [389] [632] \hold_reg_reg[4]_in
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01- 1
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1-1 1
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.names [433] [328] [280]
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|
11 0
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.names [572] [371] [648] tx_fifo_gb_reg_in
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11- 0
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--1 0
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.names \tx_fifo_mem_reg[2][1] [282]
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1 1
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.names \dpll_state_reg[0] [283]
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1 1
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1 1
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1 1
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1 1
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.names \tx_fifo_mem_reg[1][1] [287]
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1 1
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.names \tx_fifo_mem_reg[1][2] [288]
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1 1
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|
.names \tx_fifo_mem_reg[1][3] [289]
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1 1
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|
.names \tx_fifo_mem_reg[1][4] [290]
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1 1
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|
.names \tx_fifo_mem_reg[1][6] [291]
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1 1
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1 1
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1 1
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.names \tx_fifo_mem_reg[2][2] [294]
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1 1
|
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.names \tx_fifo_mem_reg[2][3] [295]
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1 1
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|
.names \tx_fifo_mem_reg[2][4] [296]
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1 1
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.names \tx_fifo_mem_reg[2][6] [297]
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1 1
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.names \tx_fifo_mem_reg[2][7] [298]
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1 1
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|
|
1 1
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.names \tx_fifo_rp_reg[1] [300]
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|
1 1
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|
.names \hold_reg_reg[0] [301]
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|
1 1
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|
.names \tx_fifo_mem_reg[1][5] [302]
|
|
1 1
|
|
.names \tx_fifo_mem_reg[2][5] [303]
|
|
1 1
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|
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|
|
11 0
|
|
.names \tx_fifo_mem_reg[3][1] [305]
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|
1 1
|
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.names \tx_fifo_mem_reg[3][6] [306]
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|
1 1
|
|
.names rx_valid_r_reg [307]
|
|
0 1
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|
.names \tx_fifo_mem_reg[3][5] [308]
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1 1
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.names change_reg [309]
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1 1
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.names \tx_fifo_mem_reg[0][0] [310]
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1 1
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.names \tx_fifo_mem_reg[0][3] [311]
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1 1
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|
.names \tx_fifo_mem_reg[0][4] [312]
|
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1 1
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.names \tx_fifo_mem_reg[0][7] [313]
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1 1
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.names \tx_fifo_mem_reg[0][2] [314]
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|
1 1
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|
.names \tx_fifo_mem_reg[3][0] [315]
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1 1
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.names \tx_fifo_mem_reg[3][2] [316]
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|
1 1
|
|
.names \tx_fifo_mem_reg[3][3] [317]
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|
1 1
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|
.names \tx_fifo_mem_reg[3][4] [318]
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1 1
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|
.names \tx_fifo_mem_reg[3][7] [319]
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|
1 1
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|
.names \rx_fifo_rp_reg[1] [320]
|
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1 1
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|
.names \hold_reg_reg[9] [321]
|
|
1 1
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|
.names [671] [631] [412] [322]
|
|
00- 1
|
|
--0 1
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|
.names \tx_fifo_mem_reg[0][6] [323]
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1 1
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|
.names \tx_fifo_mem_reg[0][5] [324]
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|
1 1
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|
.names \tx_fifo_mem_reg[0][1] [325]
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|
1 1
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.names \tx_bit_cnt_reg[1] [326]
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1 1
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|
.names [265] [595] [423] [327]
|
|
11- 0
|
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--1 0
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.names rx_sio_ce_reg [328]
|
|
1 1
|
|
.names [583] [254] [405] [329]
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11- 0
|
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.names [291] [478] we_i \tx_fifo_mem_reg[1][6]_in
|
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01- 1
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1-1 1
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|
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|
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01- 1
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1-1 1
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|
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01- 1
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|
1-1 1
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|
.names [282] [486] we_i \tx_fifo_mem_reg[2][1]_in
|
|
01- 1
|
|
1-1 1
|
|
.names [294] [481] we_i \tx_fifo_mem_reg[2][2]_in
|
|
01- 1
|
|
1-1 1
|
|
.names [295] [482] we_i \tx_fifo_mem_reg[2][3]_in
|
|
01- 1
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|
1-1 1
|
|
.names [296] [483] we_i \tx_fifo_mem_reg[2][4]_in
|
|
01- 1
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|
1-1 1
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|
.names [303] [471] we_i \tx_fifo_mem_reg[2][5]_in
|
|
01- 1
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|
1-1 1
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|
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01- 1
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1-1 1
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|
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01- 1
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1-1 1
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11 0
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|
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11 0
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1 1
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|
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|
11 0
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|
.names [687] [499] [632] \tx_fifo_rp_reg[1]_in
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01- 1
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1-1 1
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|
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|
11- 0
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--1 0
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|
11 0
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|
.names [439] [440] dout_o[5]
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11 0
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11 0
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11 0
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.names [441] [442] dout_o[1]
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11 0
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00 1
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|
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01- 1
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|
1-1 1
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|
.names [220] [152] [502] [353]
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01- 1
|
|
1-1 1
|
|
.names [223] [153] [502] [354]
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01- 1
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1-1 1
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|
.names [224] [154] [502] [355]
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01- 1
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1-1 1
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|
.names [225] [155] [502] [356]
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01- 1
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|
1-1 1
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|
.names [227] [156] [502] [357]
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01- 1
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|
1-1 1
|
|
.names [226] [157] [502] [358]
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01- 1
|
|
1-1 1
|
|
.names [221] [158] [502] [359]
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01- 1
|
|
1-1 1
|
|
.names [222] [165] [689] [360]
|
|
01- 1
|
|
1-1 1
|
|
.names [220] [166] [689] [361]
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01- 1
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|
1-1 1
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|
.names [223] [167] [689] [362]
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01- 1
|
|
1-1 1
|
|
.names [224] [168] [689] [363]
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01- 1
|
|
1-1 1
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|
.names [225] [169] [689] [364]
|
|
01- 1
|
|
1-1 1
|
|
.names [573] [590] [457] \dpll_state_reg[0]_in
|
|
111 0
|
|
.names [227] [170] [689] [366]
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|
01- 1
|
|
1-1 1
|
|
.names [226] [171] [689] [367]
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01- 1
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1-1 1
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01- 1
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|
1-1 1
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|
.names [174] [220] [504] [369]
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01- 1
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1-1 1
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|
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|
|
0 1
|
|
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|
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111 0
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|
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01- 1
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1-1 1
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.names [173] [222] [504] [373]
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01- 1
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1-1 1
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01- 1
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1-1 1
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01- 1
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1-1 1
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01- 1
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1-1 1
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01- 1
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1-1 1
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01- 1
|
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1-1 1
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|
|
11 0
|
|
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|
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00- 1
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--0 1
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11-- 0
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.names [544] [535] [462] [382]
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111 0
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111 0
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111 0
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111 0
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111 0
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111 0
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111 0
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111 0
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|
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01- 1
|
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1-1 1
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|
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01- 1
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|
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01- 1
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1-1 1
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01- 1
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1-1 1
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01- 1
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1-1 1
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|
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01- 1
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|
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1-1 1
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1-1 1
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|
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1-1 1
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|
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|
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01- 1
|
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1-1 1
|
|
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|
|
01- 1
|
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1-1 1
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|
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|
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01- 1
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1-1 1
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|
|
01- 1
|
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1-1 1
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|
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00 1
|
|
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|
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01- 1
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|
1-1 1
|
|
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00 1
|
|
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|
|
1 1
|
|
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|
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1 1
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|
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|
|
11 1
|
|
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|
|
01- 1
|
|
1-1 1
|
|
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|
|
1 1
|
|
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|
|
00 0
|
|
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11 0
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|
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01- 1
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1-1 1
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|
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|
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01- 1
|
|
1-1 1
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|
.names [222] [159] [540] [415]
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01- 1
|
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1-1 1
|
|
.names [223] [161] [540] [416]
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01- 1
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1-1 1
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|
.names [220] [160] [540] [417]
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01- 1
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1-1 1
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|
.names [224] [162] [540] [418]
|
|
01- 1
|
|
1-1 1
|
|
.names [225] [163] [540] [419]
|
|
01- 1
|
|
1-1 1
|
|
.names [227] [164] [540] [420]
|
|
01- 1
|
|
1-1 1
|
|
.names [491] [591] \tx_bit_cnt_reg[1]_in
|
|
00 1
|
|
.names [508] [648] [589] change_reg_in
|
|
00- 1
|
|
--0 1
|
|
.names [488] [595] [423]
|
|
00 1
|
|
.names [310] [523] we_i \tx_fifo_mem_reg[0][0]_in
|
|
01- 1
|
|
1-1 1
|
|
.names [325] [528] we_i \tx_fifo_mem_reg[0][1]_in
|
|
01- 1
|
|
1-1 1
|
|
.names [314] [524] we_i \tx_fifo_mem_reg[0][2]_in
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01- 1
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1-1 1
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1-1 1
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1-1 1
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1-1 1
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|
|
.names [283] [652]
|
|
0 1
|
|
.names [255] [653]
|
|
0 1
|
|
.names [510] [654]
|
|
0 1
|
|
.names [268] [655]
|
|
0 1
|
|
.names [265] [656]
|
|
0 1
|
|
.names [659] [658] [657]
|
|
00 1
|
|
.names [676] [658]
|
|
0 1
|
|
.names [660] [666] [659]
|
|
11 0
|
|
.names [683] [665] [660]
|
|
11 0
|
|
.names [662] [630] [661]
|
|
11 0
|
|
.names [663] [662]
|
|
0 1
|
|
.names [406] [663]
|
|
0 1
|
|
.names [506] [664]
|
|
0 1
|
|
.names [320] [665]
|
|
0 1
|
|
.names [684] [320] [666]
|
|
11 0
|
|
.names [681] [320] [147] [667]
|
|
111 0
|
|
.names [669] [686] [147] [668]
|
|
111 0
|
|
.names [320] [669]
|
|
0 1
|
|
.names [671] [683] [672] \rx_fifo_wp_reg[1]_in
|
|
01- 1
|
|
1-1 1
|
|
.names [679] [566] [671]
|
|
11 0
|
|
.names [678] [677] [672]
|
|
11 0
|
|
.names [674] [677] [673]
|
|
11 0
|
|
.names [675] [676] [674]
|
|
11 0
|
|
.names [668] [667] [675]
|
|
11 0
|
|
.names [606] [623] [676]
|
|
11 0
|
|
.names [307] rx_valid_r_reg_in [677]
|
|
11 1
|
|
.names [674] [678]
|
|
1 1
|
|
.names [682] [680] [679]
|
|
11 0
|
|
.names [148] [680]
|
|
0 1
|
|
.names [686] [681]
|
|
0 1
|
|
.names [685] [682]
|
|
0 1
|
|
.names [684] [683]
|
|
0 1
|
|
.names [685] [684]
|
|
1 1
|
|
.names [686] [685]
|
|
1 1
|
|
.names [183] [686]
|
|
0 1
|
|
.names [688] [687]
|
|
0 1
|
|
.names [300] [688]
|
|
0 1
|
|
.names [690] [689]
|
|
0 1
|
|
.names [503] [690]
|
|
0 1
|
|
.names [692] [691]
|
|
0 1
|
|
.names [693] [692]
|
|
1 1
|
|
.names [432] [693]
|
|
0 1
|
|
.names [584] [694]
|
|
0 1
|
|
.names [609] [695]
|
|
1 1
|
|
.names rxd_i rxd_s_reg_in
|
|
1 1
|
|
.end
|