37 lines
625 B
Verilog
37 lines
625 B
Verilog
module repwhile_test001(input [5:0] a, output [7:0] y, output [31:0] x);
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function [7:0] mylog2;
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input [31:0] value;
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begin
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mylog2 = 0;
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while (value > 0) begin
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value = value >> 1;
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mylog2 = mylog2 + 1;
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end
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end
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endfunction
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function [31:0] myexp2;
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input [7:0] value;
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begin
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myexp2 = 1;
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repeat (value)
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myexp2 = myexp2 << 1;
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end
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endfunction
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reg [7:0] y_table [63:0];
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reg [31:0] x_table [63:0];
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integer i;
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initial begin
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for (i = 0; i < 64; i = i+1) begin
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y_table[i] <= mylog2(i);
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x_table[i] <= myexp2(i);
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end
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end
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assign y = y_table[a];
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assign x = x_table[a];
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endmodule
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