144 lines
3.4 KiB
Verilog
144 lines
3.4 KiB
Verilog
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// test_simulation_techmap_and_19_tech.v
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module f1_TECH_AND18(input [17:0] in, output out);
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assign out = ∈
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endmodule
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module f1_TECH_AND4(input [3:0] in, output out);
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assign out = ∈
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endmodule
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// test_simulation_techmap_and_5_tech.v
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module f2_TECH_AND5(input [4:0] in, output out);
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assign out = ∈
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endmodule
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// test_simulation_techmap_nand_19_tech.v
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module f3_TECH_NAND18(input [17:0] in, output out);
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assign out = ~(&in);
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endmodule
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module f3_TECH_NAND4(input [3:0] in, output out);
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assign out = ~(&in);
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endmodule
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module f3_TECH_NAND2(input [1:0] in, output out);
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assign out = ~(&in);
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endmodule
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// test_simulation_techmap_nand_2_tech.v
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module f4_TECH_NAND18(input [17:0] in, output out);
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assign out = ~(&in);
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endmodule
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module f4_TECH_NAND4(input [3:0] in, output out);
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assign out = ~(&in);
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endmodule
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module f4_TECH_NAND2(input [1:0] in, output out);
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assign out = ~(&in);
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endmodule
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// test_simulation_techmap_nand_5_tech.v
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module f5_TECH_NAND18(input [17:0] in, output out);
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assign out = ~(&in);
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endmodule
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module f5_TECH_NAND4(input [3:0] in, output out);
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assign out = ~(&in);
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endmodule
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module f5_TECH_NAND2(input [1:0] in, output out);
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assign out = ~(&in);
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endmodule
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// test_simulation_techmap_nor_19_tech.v
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module f6_TECH_NOR18(input [17:0] in, output out);
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assign out = ~(|in);
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endmodule
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module f6_TECH_NOR4(input [3:0] in, output out);
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assign out = ~(|in);
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endmodule
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module f6_TECH_NOR2(input [1:0] in, output out);
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assign out = ~(|in);
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endmodule
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// test_simulation_techmap_nor_2_tech.v
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module f7_TECH_NOR18(input [17:0] in, output out);
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assign out = ~(|in);
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endmodule
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module f7_TECH_NOR4(input [3:0] in, output out);
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assign out = ~(|in);
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endmodule
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module f7_TECH_NOR2(input [1:0] in, output out);
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assign out = ~(|in);
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endmodule
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// test_simulation_techmap_nor_5_tech.v
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module f8_TECH_NOR18(input [17:0] in, output out);
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assign out = ~(|in);
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endmodule
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module f8_TECH_NOR4(input [3:0] in, output out);
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assign out = ~(|in);
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endmodule
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module f8_TECH_NOR2(input [1:0] in, output out);
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assign out = ~(|in);
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endmodule
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// test_simulation_techmap_or_19_tech.v
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module f9_TECH_OR18(input [17:0] in, output out);
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assign out = |in;
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endmodule
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module f9_TECH_OR4(input [3:0] in, output out);
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assign out = |in;
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endmodule
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// test_simulation_techmap_or_5_tech.v
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module f10_TECH_OR5(input [4:0] in, output out);
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assign out = |in;
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endmodule
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// test_simulation_techmap_xnor_2_tech.v
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module f11_TECH_XOR5(input [4:0] in, output out);
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assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
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endmodule
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module f11_TECH_XOR2(input [1:0] in, output out);
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assign out = in[0] ^ in[1];
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endmodule
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// test_simulation_techmap_xnor_5_tech.v
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module f12_TECH_XOR5(input [4:0] in, output out);
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assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
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endmodule
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module f12_TECH_XOR2(input [1:0] in, output out);
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assign out = in[0] ^ in[1];
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endmodule
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// test_simulation_techmap_xor_19_tech.v
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module f13_TECH_XOR2(input [1:0] in, output out);
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assign out = in[0] ^ in[1];
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endmodule
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// test_simulation_techmap_xor_2_tech.v
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module f14_TECH_XOR5(input [4:0] in, output out);
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assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
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endmodule
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module f14_TECH_XOR2(input [1:0] in, output out);
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assign out = in[0] ^ in[1];
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endmodule
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// test_simulation_techmap_xor_5_tech.v
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module f15_TECH_XOR5(input [4:0] in, output out);
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assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
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endmodule
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module f15_TECH_XOR2(input [1:0] in, output out);
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assign out = in[0] ^ in[1];
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endmodule
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