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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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33f3a991b5
OpenFPGA
/
vpr7_x2p
/
vpr
/
SRC
/
fpga_x2p
/
router
History
tangxifan
95674c4687
added Switch Block SubType and SubFs for tileable rr_graph generation
2019-07-02 10:00:02 -06:00
..
fpga_x2p_pb_rr_graph.c
bug fixing for memory leaking in allocating pb_rr_graph and power estimation
2019-06-15 12:23:36 -06:00
fpga_x2p_pb_rr_graph.h
Update VPR7 X2P with new engine
2019-04-26 12:23:47 -06:00
fpga_x2p_router.c
added Switch Block SubType and SubFs for tileable rr_graph generation
2019-07-02 10:00:02 -06:00
fpga_x2p_router.h
Update VPR7 X2P with new engine
2019-04-26 12:23:47 -06:00