riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
OpenFPGA/openfpga
History
tangxifan 33972fc0ec [FPGA-Bitstream] Upgraded bitstream writer to support QuickLogic memory bank using shift registers 2021-09-30 21:05:41 -07:00
..
src [FPGA-Bitstream] Upgraded bitstream writer to support QuickLogic memory bank using shift registers 2021-09-30 21:05:41 -07:00
CMakeLists.txt [Tool] Deploy pin constraints to preconfig Verilog module generation 2021-01-19 16:56:30 -07:00