362 lines
14 KiB
ReStructuredText
362 lines
14 KiB
ReStructuredText
.. _run_fpga_task:
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OpenFPGA Task
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---------------
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Tasks provide a framework for running the :ref:`run_fpga_flow` on
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multiple benchmarks, architectures, and set of OpenFPGA parameters.
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The structure of the framework is very similar to
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`VTR-Tasks <https://docs.verilogtorouting.org/en/latest/vtr/tasks/>`_
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implementation with additional functionality and minor file extension changes.
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Task Directory
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~~~~~~~~~~~~~~
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The tasks are stored in a ``TASK_DIRECTORY``, which by default points to
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``${OPENFPGA_PATH}/openfpga_flow/tasks``. Every directory or sub-directory in
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task directory consisting of ``../config/task.conf`` file can be referred to as a
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task.
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To create as task name called ``basic_flow`` following directory has to exist::
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${TASK_DIRECTORY}/basic_flow/conf/task.conf
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Similarly ``regression/regression_quick`` expect following structure::
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${TASK_DIRECTORY}/regression/regression_quick/conf/task.conf
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Running OpenFPGA Task:
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~~~~~~~~~~~~~~~~~~~~~~
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At a minimum ``open_fpga_flow.py`` requires following command-line arguments::
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open_fpga_flow.py <task1_name> <task2_name> ... [<options>]
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where:
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* ``<task_name>`` is the name of the task to run
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* ``<options>`` Other command line arguments described below
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Command-line Options
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~~~~~~~~~~~~~~~~~~~~
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.. option:: --maxthreads <number_of_threads>
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This option defines the number of threads to run while executing task.
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Each combination of architecture, benchmark and set of OpenFPGA Flow options
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runs in a individual thread.
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.. option:: --skip_thread_logs
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Passsing this option skips printing logs from each OpenFPGA Flow script run.
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.. option:: --exit_on_fail
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Passsing this option exits the OpenFPGA task script with returncode 1,
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if any threads fail to execute successfully. It is mainly used to while
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performing regression test.
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.. option:: --test_run
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This option allows to debug OpenFPGA Task script
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by skiping actual execution of OpenFPGA flow .
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Passing this option prints the list of
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commnad generated to execute using OpenFPGA flow.
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.. option:: --debug
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To enable detailed log printing.
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Creating a new OpenFPGA Task
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Create the folder ``${TASK_DIRECTORY}/<task_name>``
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- Create a file ``${TASK_DIRECTORY}/<task_name>/config/task.conf`` in it
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- Configure the task as explained in :ref:`Configuring a new OpenFPGA Task`
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Configuring a new OpenFPGA Task
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The task configuration file ``task.conf`` consists of ``GENERAL``,
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``ARCHITECTURES``, ``BENCHMARKS``, ``SYNTHESIS_PARAM`` and
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``SCRIPT_PARAM_<var_name>`` sections.
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Declaring all the above sections are mandatory.
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.. note::
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The configuration file supports all the OpenFPGA Variables refer
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:ref:`openfpga-variables` section to know more. Variable in the configuration
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file is declared as ``${PATH:<variable_name>}``
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General Section
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^^^^^^^^^^^^^^^
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.. option:: fpga_flow=<yosys_vpr|vpr_blif|yosys>
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This option defines which OpenFPGA flow to run. By default ``yosys_vpr`` is executed.
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.. option:: power_analysis=<true|false>
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Specifies whether to perform power analysis or not.
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.. option:: power_tech_file=<path_to_tech_XML_file>
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Declares which tech XML file to use while performing Power Analysis.
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.. option:: spice_output=<true|false>
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Setting up this variable generates Spice Netlist at the end of the flow.
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Equivalent of passing ``--vpr_fpga_spice`` command to :ref:`run_fpga_flow`
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.. option:: verilog_output=<true|false>
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Setting up this variable generates Verilog Netlist at the end of the flow.
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Equivalent of passing ``--vpr_fpga_spice`` command to :ref:`run_fpga_flow`
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.. option:: timeout_each_job=<true|false>
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Specifies the timeout for each :ref:`run_fpga_flow` execution. Default is set to ``20 min.``
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.. option:: verific=<true|false>
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Specifies to use Verific as a frontend for Yosys while running a yosys_vpr flow.
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The following standards are used by default for reading input HDL files:
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* Verilog - ``vlog95``
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* System Verilog - ``sv2012``
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* VHDL - ``vhdl2008``
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The option should be used only with custom Yosys template containing Verific commands.
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OpenFPGA_SHELL Sections
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^^^^^^^^^^^^^^^^^^^^^^^
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User can specify OpenFPGA_SHELL options in this section.
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Architectures Sections
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^^^^^^^^^^^^^^^^^^^^^^
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User can define the list of architecture files in this section.
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.. option:: arch<arch_label>=<xml_architecture_file_path>
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The ``arch_label`` variable can be any number of string without
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white-spaces. ``xml_architecture_file_path`` is path to the actual XML
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architecture file
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.. note::
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In the final OpenFPGA Task result, the architecture will be referred by its
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``arch_label``.
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Benchmarks Sections
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^^^^^^^^^^^^^^^^^^^
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User can define the list of benchmarks files in this section.
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.. option:: bench<bench_label>=<list_of_files_in_benchmark>
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The ``bench_label`` variable can be any number of string without
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white-spaces. ``list_of_files_in_benchmark`` is a list of benchmark HDL files paths.
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For Example following code shows how to define a benchmarks,
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with a single file, multiple files and files added from a specific directory.
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.. code-block:: text
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[BENCHMARKS]
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# To declare single benchmark file
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bench_design1=${BENCH_PATH}/design/top.v
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# To declare multiple benchmark file
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bench_design2=${BENCH_PATH}/design/top.v,${BENCH_PATH}/design/sub_module.v
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# To add all files in specific directory to the benchmark
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bench_design3=${BENCH_PATH}/design/top.v,${BENCH_PATH}/design/lib/*.v
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.. note::
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``bench_label`` is referred again in ``Synthesis_Param`` section to
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provide additional information about benchmark
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Synthesis Parameter Sections
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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User can define extra parameters for each benchmark in the
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``BENCHMARKS`` sections.
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.. option:: bench<bench_label>_top=<Top_Module_Name>
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This option defines the Top Level module name for ``bench_label`` benchmark.
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By default, the top-level module name is considered as a ``top``.
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.. option:: bench<bench_label>_yosys=<yosys_template_file>
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This config defines Yosys template script file.
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.. option:: bench<bench_label>_chan_width=<chan_width_to_use>
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In case of running fixed channel width routing for each benchmark,
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this option defines the channel width to be used for ``bench_label``
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benchmark
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.. option:: bench<bench_label>_act=<activity_file_path>
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In case of running ``blif_vpr_flow`` this option provides the activity files
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to be used to generate testbench for ``bench_label`` benchmark
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.. note:: This file is required only when the ``power_analysis`` option in the general section is enabled. Otherwise, it is optional
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.. option:: bench<bench_label>_verilog=<source_verilog_file_path>
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In case of running ``blif_vpr_flow`` with verification this option provides
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the source Verilog design for ``bench_label`` benchmark to be used
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while verification.
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.. option:: bench<bench_label>_read_verilog_options=<Options>
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This config defines the ``read_verilog`` command options for ``bench_label`` benchmark.
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.. option:: bench<bench_label>_yosys_args=<Arguments>
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This config defines Yosys arguments to be used in QuickLogic synthesis script for ``bench_label`` benchmark.
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.. option:: bench<bench_label>_yosys_dff_map_verilog=<dff_technology_file_path>
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This config defines DFF technology file to be used in technology mapping for ``bench_label`` benchmark.
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.. option:: bench<bench_label>_yosys_bram_map_verilog=<bram_technology_file_path>
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This config defines BRAM technology file to be used in technology mapping for ``bench_label`` benchmark.
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.. option:: bench<bench_label>_yosys_bram_map_rules=<bram_technology_rules_file_path>
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This config defines BRAM technology rules file to be used in technology mapping for ``bench_label`` benchmark. This config should be used with ``bench<bench_label>_yosys_bram_map_verilog`` config.
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.. option:: bench<bench_label>_yosys_dsp_map_verilog=<dsp_technology_file_path>
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This config defines DSP technology file to be used in technology mapping for ``bench_label`` benchmark.
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.. option:: bench<bench_label>_yosys_dsp_map_parameters=<dsp_mapping_parameters>
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This config defines DSP technology parameters to be used in technology mapping for ``bench_label`` benchmark. This config should be used with ``bench<bench_label>_yosys_dsp_map_verilog`` config.
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.. option:: bench<bench_label>_verific_include_dir=<include_dir_path>
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This config defines include directory path for ``bench_label`` benchmark. Verific will search in this directory to find included files. If there are multiple paths then they can be provided as a comma separated list.
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.. option:: bench<bench_label>_verific_library_dir=<library_dir_path>
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This config defines library directory path for ``bench_label`` benchmark. Verific will search in this directory to find undefined modules. If there are multiple paths then they can be provided as a comma separated list.
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.. option:: bench<bench_label>_verific_verilog_standard=<-vlog95|-vlog2k>
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The config specifies Verilog language standard to be used while reading the Verilog files for ``bench_label`` benchmark.
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.. option:: bench<bench_label>_verific_systemverilog_standard=<-sv2005|-sv2009|-sv2012>
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The config specifies SystemVerilog language standard to be used while reading the SystemVerilog files for ``bench_label`` benchmark.
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.. option:: bench<bench_label>_verific_vhdl_standard=<-vhdl87|-vhdl93|-vhdl2k|-vhdl2008>
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The config specifies VHDL language standard to be used while reading the VHDL files for ``bench_label`` benchmark.
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.. option:: bench<bench_label>_verific_read_lib_name<lib_label>=<lib_name>
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The ``lib_label`` variable can be any number of string without white-spaces. The config specifies library name for ``bench_label`` benchmark where Verilog/SystemVerilog/VHDL files specified by ``bench<bench_label>_verific_read_lib_src<lib_label>`` config will be loaded. This config should be used only with ``bench<bench_label>_verific_read_lib_src<lib_label>`` config.
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.. option:: bench<bench_label>_verific_read_lib_src<lib_label>=<library_src_files>
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The ``lib_label`` variable can be any number of string without white-spaces. The config specifies Verilog/SystemVerilog/VHDL files to be loaded into library specified by ``bench<bench_label>_verific_read_lib_name<lib_label>`` config for ``bench_label`` benchmark. The ``library_src_files`` should be the source files names separated by commas. This config should be used only with ``bench<bench_label>_verific_read_lib_name<lib_label>`` config.
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.. option:: bench<bench_label>_verific_search_lib=<lib_name>
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The config specifies library name for ``bench_label`` benchmark from where Verific will look up for external definitions while reading HDL files.
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.. option:: bench<bench_label>_yosys_cell_sim_verilog=<verilog_files>
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The config specifies Verilog files for ``bench_label`` benchmark which should be separated by comma.
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.. option:: bench<bench_label>_yosys_cell_sim_systemverilog=<systemverilog_files>
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The config specifies SystemVerilog files for ``bench_label`` benchmark which should be separated by comma.
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.. option:: bench<bench_label>_yosys_cell_sim_vhdl=<vhdl_files>
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The config specifies VHDL files for ``bench_label`` benchmark which should be separated by comma.
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.. option:: bench<bench_label>_yosys_blackbox_modules=<blackbox_modules>
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The config specifies blackbox modules names for ``bench_label`` benchmark which should be separated by comma (usually these are the modules defined in files specified with bench<bench_label>_yosys_cell_sim_<verilog/systemverilog/vhdl> option).
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.. note::
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The following configs might be common for all benchmarks:
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* ``bench<bench_label>_yosys``
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* ``bench<bench_label>_chan_width``
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* ``bench<bench_label>_read_verilog_options``
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* ``bench<bench_label>_yosys_args``
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* ``bench<bench_label>_yosys_bram_map_rules``
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* ``bench<bench_label>_yosys_bram_map_verilog``
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* ``bench<bench_label>_yosys_cell_sim_verilog``
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* ``bench<bench_label>_yosys_cell_sim_systemverilog``
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* ``bench<bench_label>_yosys_cell_sim_vhdl``
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* ``bench<bench_label>_yosys_blackbox_modules``
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* ``bench<bench_label>_yosys_dff_map_verilog``
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* ``bench<bench_label>_yosys_dsp_map_parameters``
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* ``bench<bench_label>_yosys_dsp_map_verilog``
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* ``bench<bench_label>_verific_verilog_standard``
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* ``bench<bench_label>_verific_systemverilog_standard``
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* ``bench<bench_label>_verific_vhdl_standard``
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* ``bench<bench_label>_verific_include_dir``
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* ``bench<bench_label>_verific_library_dir``
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* ``bench<bench_label>_verific_search_lib``
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*The following syntax should be used to define common config:* ``bench_<config_name>_common``
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Script Parameter Sections
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^^^^^^^^^^^^^^^^^^^^^^^^^
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The script parameter section lists set of commnad line pararmeters to be passed to :ref:`run_fpga_flow` script. The section name is defines as ``SCRIPT_PARAM_<parameter_set_label>`` where `parameter_set_label` can be any word without white spaces.
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The section is referred with ``parameter_set_label`` in the final result file.
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For example following code Specifies the two sets (``Fixed_Routing_30`` and ``Fixed_Routing_50``) of :ref:`run_fpga_flow` arguments.
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.. code-block:: text
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[SCRIPT_PARAM_Fixed_Routing_30]
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# Execute fixed routing with channel with 30
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fix_route_chan_width=30
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[SCRIPT_PARAM_Fixed_Routing_50]
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# Execute fixed routing with channel with 50
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fix_route_chan_width=50
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Example Task Configuration File
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. code-block:: text
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[GENERAL]
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spice_output=false
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verilog_output=false
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power_analysis = true
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power_tech_file = ${PATH:TECH_PATH}/winbond90nm/winbond90nm_power_properties.xml
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timeout_each_job = 20*60
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[ARCHITECTURES]
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arch0=${PATH:ARCH_PATH}/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml
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[BENCHMARKS]
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bench0=${PATH:BENCH_PATH}/MCNC_Verilog/s298/s298.v
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bench1=${PATH:BENCH_PATH}/MCNC_Verilog/elliptic/elliptic.v
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[SYNTHESIS_PARAM]
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bench0_top = s298
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bench1_top = elliptic
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[SCRIPT_PARAM_Slack_30]
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min_route_chan_width=1.3
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[SCRIPT_PARAM_Slack_80]
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min_route_chan_width=1.8
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