tangxifan 32fc0a1692 [FPGA-Verilog] Upgrading verilog testbench generator for QuickLogic memory bank using BL/WL shift register		2021-10-02 17:25:27 -07:00
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src	[FPGA-Verilog] Upgrading verilog testbench generator for QuickLogic memory bank using BL/WL shift register	2021-10-02 17:25:27 -07:00
CMakeLists.txt	[Tool] Deploy pin constraints to preconfig Verilog module generation	2021-01-19 16:56:30 -07:00