tangxifan 477a522885 [HDL] Rename tech lib to be consistent with arch name changes		2021-03-20 18:08:03 -06:00
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k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt	[HDL] Rename tech lib to be consistent with arch name changes	2021-03-20 18:08:03 -06:00
k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v	[HDL] Rename tech lib to be consistent with arch name changes	2021-03-20 18:08:03 -06:00
k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_cell_sim.v	[HDL] Rename tech lib to be consistent with arch name changes	2021-03-20 18:08:03 -06:00
k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v	[HDL] Rename tech lib to be consistent with arch name changes	2021-03-20 18:08:03 -06:00
openfpga_adders_sim.v	[HDL] Add SPRAM module to generic yosys tech lib for openfpga usage	2021-03-16 18:04:31 -06:00
openfpga_arith_map.v	[Script] Rename yosys script supporting bram and restructure techlib files	2021-03-16 16:16:53 -06:00
openfpga_brams.txt	[Script] Rename yosys script supporting bram and restructure techlib files	2021-03-16 16:16:53 -06:00
openfpga_brams_map.v	[Script] Rename yosys script supporting bram and restructure techlib files	2021-03-16 16:16:53 -06:00
openfpga_brams_sim.v	[HDL] Add an adhoc yosys technology library for a heterogeneous FPGA architecture	2021-03-17 15:09:12 -06:00