293 lines
9.4 KiB
Verilog
293 lines
9.4 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// Forward Discrete Cosine Transform and ZigZag unit ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: fdct.v,v 1.3 2002-10-31 12:50:03 rherveille Exp $
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//
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// $Date: 2002-10-31 12:50:03 $
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// $Revision: 1.3 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/10/23 09:06:59 rherveille
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// Improved many files.
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// Fixed some bugs in Run-Length-Encoder.
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// Removed dependency on ud_cnt and ro_cnt.
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// Started (Motion)JPEG hardware encoder project.
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//
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//synopsys translate_off
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`include "timescale.v"
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//synopsys translate_on
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module fdct(clk, ena, rst, dstrb, din, dout, douten);
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//
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// parameters
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//
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////////////////////////////////////////////////////////////////////
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// //
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// ITU-T.81, ITU-T.83 & Coefficient resolution notes //
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// //
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////////////////////////////////////////////////////////////////////
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// //
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// Worst case error (all input values -128) is //
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// zero (i.e. no errors) when using 15bit coefficients //
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// //
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// Using less bits for the coefficients produces a biterror //
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// approx. equal to (15 - used_coefficient-bits). //
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// i.e. 14bit coefficients, errors in dout-bit[0] only //
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// 13bit coefficients, errors in dout-bits[1:0] //
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// 12bit coefficients, errors in dout-bits[2:0] etc. //
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// Tests with real non-continous tone image data have shown that //
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// even when using 13bit coefficients errors remain in the lsb //
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// only (i.e. dout-bit[0] //
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// //
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// The amount of coefficient-bits needed is dependent on the //
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// desired quality. //
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// The JPEG-standard compliance specs.(ITU-T.83) prescribe //
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// that the output of the combined DCT AND Quantization unit //
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// shall not exceed 1 for the desired quality. //
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// //
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// This means for high quantization levels, lesser bits //
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// for the DCT unit can be used. //
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// //
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// Looking at the recommended "quantization tables for generic //
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// compliance testing of DCT-based processes" (ITU-T.83 annex B) //
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// it can be noticed that relatively large quantization values //
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// are being used. Errors in the lower-order bits should //
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// therefore not be visible. //
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// For certain applications some of the lower-order bits could //
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// actually be discarded. When looking at the luminance and //
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// chrominance example quantization tables (ITU-T.81 annex K) //
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// it can be seen that the smallest quantization value is ten //
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// (qnt_val_min = 10). This means that the lowest 2bits can be //
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// discarded (set to zero '0') without having any effect on the //
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// final result. In this example 11 bit or 12 bit coefficients //
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// would be sufficient. //
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// //
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////////////////////////////////////////////////////////////////////
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parameter coef_width = 11;
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parameter di_width = 8;
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parameter do_width = 12;
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//
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// inputs & outputs
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//
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input clk; // system clock
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input ena; // clock enable
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input rst; // active low asynchronous reset
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input dstrb; // data-strobe. Present dstrb 1clk-cycle before data block
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input [di_width-1:0] din;
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output [do_width-1:0] dout;
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output douten; // data-out enable
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//
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// variables
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//
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wire doe;
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wire [do_width -1:0] // results from DCT module
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res00, res01, res02, res03, res04, res05, res06, res07,
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res10, res11, res12, res13, res14, res15, res16, res17,
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res20, res21, res22, res23, res24, res25, res26, res27,
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res30, res31, res32, res33, res34, res35, res36, res37,
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res40, res41, res42, res43, res44, res45, res46, res47,
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res50, res51, res52, res53, res54, res55, res56, res57,
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res60, res61, res62, res63, res64, res65, res66, res67,
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res70, res71, res72, res73, res74, res75, res76, res77;
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//
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// module body
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//
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// Hookup DCT module
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dct #(coef_width, di_width, do_width)
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dct_mod(
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.clk(clk),
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.ena(ena),
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.rst(rst),
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.dstrb(dstrb),
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.din(din),
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.dout_00(res00),
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.dout_01(res01),
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.dout_02(res02),
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.dout_03(res03),
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.dout_04(res04),
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.dout_05(res05),
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.dout_06(res06),
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.dout_07(res07),
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.dout_10(res10),
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.dout_11(res11),
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.dout_12(res12),
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.dout_13(res13),
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.dout_14(res14),
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.dout_15(res15),
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.dout_16(res16),
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.dout_17(res17),
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.dout_20(res20),
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.dout_21(res21),
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.dout_22(res22),
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.dout_23(res23),
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.dout_24(res24),
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.dout_25(res25),
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.dout_26(res26),
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.dout_27(res27),
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.dout_30(res30),
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.dout_31(res31),
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.dout_32(res32),
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.dout_33(res33),
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.dout_34(res34),
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.dout_35(res35),
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.dout_36(res36),
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.dout_37(res37),
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.dout_40(res40),
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.dout_41(res41),
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.dout_42(res42),
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.dout_43(res43),
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.dout_44(res44),
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.dout_45(res45),
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.dout_46(res46),
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.dout_47(res47),
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.dout_50(res50),
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.dout_51(res51),
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.dout_52(res52),
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.dout_53(res53),
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.dout_54(res54),
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.dout_55(res55),
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.dout_56(res56),
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.dout_57(res57),
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.dout_60(res60),
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.dout_61(res61),
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.dout_62(res62),
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.dout_63(res63),
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.dout_64(res64),
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.dout_65(res65),
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.dout_66(res66),
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.dout_67(res67),
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.dout_70(res70),
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.dout_71(res71),
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.dout_72(res72),
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.dout_73(res73),
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.dout_74(res74),
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.dout_75(res75),
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.dout_76(res76),
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.dout_77(res77),
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.douten(doe)
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);
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// Hookup ZigZag unit
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zigzag zigzag_mod(
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.clk(clk),
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.ena(ena),
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.dstrb(doe),
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.din_00(res00),
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.din_01(res01),
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.din_02(res02),
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.din_03(res03),
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.din_04(res04),
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.din_05(res05),
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.din_06(res06),
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.din_07(res07),
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.din_10(res10),
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.din_11(res11),
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.din_12(res12),
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.din_13(res13),
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.din_14(res14),
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.din_15(res15),
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.din_16(res16),
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.din_17(res17),
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.din_20(res20),
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.din_21(res21),
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.din_22(res22),
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.din_23(res23),
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.din_24(res24),
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.din_25(res25),
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.din_26(res26),
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.din_27(res27),
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.din_30(res30),
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.din_31(res31),
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.din_32(res32),
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.din_33(res33),
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.din_34(res34),
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.din_35(res35),
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.din_36(res36),
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.din_37(res37),
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.din_40(res40),
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.din_41(res41),
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.din_42(res42),
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.din_43(res43),
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.din_44(res44),
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.din_45(res45),
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.din_46(res46),
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.din_47(res47),
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.din_50(res50),
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.din_51(res51),
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.din_52(res52),
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.din_53(res53),
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.din_54(res54),
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.din_55(res55),
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.din_56(res56),
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.din_57(res57),
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.din_60(res60),
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.din_61(res61),
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.din_62(res62),
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.din_63(res63),
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.din_64(res64),
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.din_65(res65),
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.din_66(res66),
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.din_67(res67),
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.din_70(res70),
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.din_71(res71),
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.din_72(res72),
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.din_73(res73),
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.din_74(res74),
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.din_75(res75),
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.din_76(res76),
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.din_77(res77),
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.dout(dout),
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.douten(douten)
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);
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endmodule
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