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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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307ef58c45
OpenFPGA
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openfpga
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tangxifan
e61e7167b3
update circuit model names in the example tree-like MUX architecture
2020-04-07 11:27:16 -06:00
..
src
update VPR7 to support global I/O ports
2020-04-06 20:44:00 -06:00
test_blif
add missing files for micro benchmarks
2020-03-20 11:08:55 -06:00
test_openfpga_arch
update circuit model names in the example tree-like MUX architecture
2020-04-07 11:27:16 -06:00
test_script
Add test cases about using standard cell mux2
2020-04-07 11:12:47 -06:00
test_vpr_arch
add support on packable/unpackable modes in VPR architecture
2020-04-06 16:07:49 -06:00
CMakeLists.txt
add simulation ini file writer
2020-02-27 18:01:47 -07:00