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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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2f434fd4d3
OpenFPGA
/
openfpga_flow
/
tasks
/
quicklogic_tests
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tangxifan
49fa783914
[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases
2022-09-29 10:45:27 -07:00
..
counter_5clock_test
/config
Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
2022-01-21 02:21:00 +05:00
flow_test
/config
[test] now use a fixed routing channel width for quicklogic tests
2022-09-20 12:25:40 -07:00
lut_adder_test
/config
[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases
2022-09-29 10:45:27 -07:00
sdc_controller_test
/config
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
2022-01-17 13:21:29 +05:00