tangxifan 2e3a811f4f critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results		2020-04-18 21:04:46 -06:00
..
OpenFPGAShellScripts	add duplicated_grid_pin test case to Travis CI	2020-04-12 20:10:51 -06:00
SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	add register chain and scan chain to Travis CI	2020-04-12 15:28:22 -06:00
arch	minor update on arch to use auto layout sizing	2020-04-18 18:43:56 -06:00
benchmarks	Added XML and benchmarks for testing	2020-04-06 00:32:06 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
misc	Updated openfpga_flow and task file to support sheel run	2020-04-06 00:34:36 -06:00
openfpga_arch	add mcnc big20 test cases and start debugging	2020-04-18 19:25:16 -06:00
scripts	BugFix: The filename in the previous commit	2020-04-15 12:44:22 -06:00
tasks	critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results	2020-04-18 21:04:46 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00