242 lines
9.4 KiB
C++
242 lines
9.4 KiB
C++
/***************************************************************************************
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* Output fabric key of Module Graph to file formats
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***************************************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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#include "vtr_time.h"
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/* Headers from openfpgautil library */
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#include "command_exit_codes.h"
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#include "openfpga_digest.h"
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/* Headers from archopenfpga library */
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#include "fabric_key_writer.h"
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#include "memory_utils.h"
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#include "openfpga_naming.h"
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#include "write_xml_fabric_key.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/***************************************************************************************
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* Add module-level keys to fabric key
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***************************************************************************************/
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static int add_module_keys_to_fabric_key(const ModuleManager& module_manager,
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const ModuleId& curr_module,
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FabricKey& fabric_key) {
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/* Bypass top-level module */
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std::string module_name = module_manager.module_name(curr_module);
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if (module_name == generate_fpga_top_module_name() ||
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module_name == generate_fpga_core_module_name()) {
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return CMD_EXEC_SUCCESS;
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}
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/* Bypass modules which does not have any configurable children */
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if (module_manager.configurable_children(curr_module).empty()) {
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return CMD_EXEC_SUCCESS;
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}
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/* Now create the module and add subkey one by one */
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FabricKeyModuleId key_module_id = fabric_key.create_module(module_name);
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if (!key_module_id) {
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return CMD_EXEC_FATAL_ERROR;
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}
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size_t num_config_child =
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module_manager.configurable_children(curr_module).size();
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for (size_t ichild = 0; ichild < num_config_child; ++ichild) {
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ModuleId child_module =
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module_manager.configurable_children(curr_module)[ichild];
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size_t child_instance =
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module_manager.configurable_child_instances(curr_module)[ichild];
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FabricSubKeyId sub_key = fabric_key.create_module_key(key_module_id);
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fabric_key.set_sub_key_name(sub_key,
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module_manager.module_name(child_module));
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fabric_key.set_sub_key_value(sub_key, child_instance);
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if (false ==
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module_manager.instance_name(curr_module, child_module, child_instance)
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.empty()) {
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fabric_key.set_sub_key_alias(
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sub_key, module_manager.instance_name(curr_module, child_module,
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child_instance));
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}
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}
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return CMD_EXEC_SUCCESS;
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}
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/***************************************************************************************
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* Write the fabric key of top module to an XML file
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* We will use the writer API in libfabrickey
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*
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* Return 0 if successful
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* Return 1 if there are more serious bugs in the architecture
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* Return 2 if fail when creating files
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***************************************************************************************/
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int write_fabric_key_to_xml_file(
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const ModuleManager& module_manager, const std::string& fname,
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const ConfigProtocol& config_protocol,
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const MemoryBankShiftRegisterBanks& blwl_sr_banks,
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const bool& include_module_keys, const bool& verbose) {
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int err_code = CMD_EXEC_SUCCESS;
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std::string timer_message =
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std::string("Write fabric key to XML file '") + fname + std::string("'");
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std::string dir_path = format_dir_path(find_path_dir_name(fname));
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/* Create directories */
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create_directory(dir_path);
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/* Start time count */
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vtr::ScopedStartFinishTimer timer(timer_message);
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/* Use default name if user does not provide one */
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VTR_ASSERT(true != fname.empty());
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/* Find top-level module */
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std::string top_module_name = generate_fpga_top_module_name();
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ModuleId top_module = module_manager.find_module(top_module_name);
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std::string core_module_name = generate_fpga_core_module_name();
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ModuleId core_module = module_manager.find_module(core_module_name);
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if (!module_manager.valid_module_id(top_module) &&
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!module_manager.valid_module_id(core_module)) {
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VTR_LOGV_ERROR(
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verbose, "Unable to find the top-level/core-level module '%s' or '%s'!\n",
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top_module_name.c_str(), core_module_name.c_str());
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return CMD_EXEC_FATAL_ERROR;
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}
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if (module_manager.valid_module_id(top_module) &&
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module_manager.valid_module_id(core_module)) {
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top_module = core_module;
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}
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/* Build a fabric key database by visiting all the configurable children */
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FabricKey fabric_key;
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size_t num_keys = module_manager.configurable_children(top_module).size();
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fabric_key.reserve_keys(num_keys);
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size_t num_regions = module_manager.regions(top_module).size();
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fabric_key.reserve_regions(num_regions);
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/* Create regions and build a id map */
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std::map<ConfigRegionId, FabricRegionId> region_id_map;
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for (const ConfigRegionId& config_region :
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module_manager.regions(top_module)) {
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FabricRegionId fabric_region = fabric_key.create_region();
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region_id_map[config_region] = fabric_region;
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}
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/* Create regions for the keys and load keys by region */
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for (const ConfigRegionId& config_region :
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module_manager.regions(top_module)) {
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/* Must have a valid one-to-one region mapping */
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auto result = region_id_map.find(config_region);
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VTR_ASSERT_SAFE(result != region_id_map.end());
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FabricRegionId fabric_region = result->second;
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/* Each configuration protocol has some child which should not be in the
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* list. They are typically decoders */
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size_t curr_region_num_config_child =
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module_manager.region_configurable_children(top_module, config_region)
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.size();
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size_t num_child_to_skip =
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estimate_num_configurable_children_to_skip_by_config_protocol(
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config_protocol, curr_region_num_config_child);
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curr_region_num_config_child -= num_child_to_skip;
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fabric_key.reserve_region_keys(fabric_region, curr_region_num_config_child);
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for (size_t ichild = 0; ichild < curr_region_num_config_child; ++ichild) {
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ModuleId child_module = module_manager.region_configurable_children(
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top_module, config_region)[ichild];
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size_t child_instance =
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module_manager.region_configurable_child_instances(
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top_module, config_region)[ichild];
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vtr::Point<int> child_coord =
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module_manager.region_configurable_child_coordinates(
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top_module, config_region)[ichild];
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FabricKeyId key = fabric_key.create_key();
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fabric_key.set_key_name(key, module_manager.module_name(child_module));
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fabric_key.set_key_value(key, child_instance);
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if (false ==
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module_manager.instance_name(top_module, child_module, child_instance)
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.empty()) {
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fabric_key.set_key_alias(
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key, module_manager.instance_name(top_module, child_module,
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child_instance));
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}
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/* Add key coordinate */
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fabric_key.set_key_coordinate(key, child_coord);
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/* Add keys to the region */
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fabric_key.add_key_to_region(fabric_region, key);
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}
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}
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/* Skip invalid region, some architecture may not have BL/WL banks */
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if (0 < blwl_sr_banks.regions().size()) {
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/* Add BL shift register bank information, if there is any */
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for (const ConfigRegionId& config_region :
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module_manager.regions(top_module)) {
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auto result = region_id_map.find(config_region);
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/* Must have a valid one-to-one region mapping */
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VTR_ASSERT_SAFE(result != region_id_map.end());
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FabricRegionId fabric_region = result->second;
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for (const FabricBitLineBankId& bank :
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blwl_sr_banks.bl_banks(config_region)) {
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FabricBitLineBankId fabric_bank =
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fabric_key.create_bl_shift_register_bank(fabric_region);
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for (const BasicPort& data_port :
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blwl_sr_banks.bl_bank_data_ports(config_region, bank)) {
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fabric_key.add_data_port_to_bl_shift_register_bank(
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fabric_region, fabric_bank, data_port);
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}
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}
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}
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/* Add WL shift register bank information, if there is any */
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for (const ConfigRegionId& config_region :
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module_manager.regions(top_module)) {
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auto result = region_id_map.find(config_region);
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/* Must have a valid one-to-one region mapping */
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VTR_ASSERT_SAFE(result != region_id_map.end());
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FabricRegionId fabric_region = result->second;
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for (const FabricWordLineBankId& bank :
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blwl_sr_banks.wl_banks(config_region)) {
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FabricWordLineBankId fabric_bank =
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fabric_key.create_wl_shift_register_bank(fabric_region);
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for (const BasicPort& data_port :
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blwl_sr_banks.wl_bank_data_ports(config_region, bank)) {
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fabric_key.add_data_port_to_wl_shift_register_bank(
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fabric_region, fabric_bank, data_port);
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}
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}
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}
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}
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VTR_LOGV(verbose, "Created %lu regions and %lu keys for the top module %s.\n",
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num_regions, num_keys, top_module_name.c_str());
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/* Output module subkeys if specified */
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if (include_module_keys) {
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for (ModuleId submodule : module_manager.modules()) {
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err_code =
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add_module_keys_to_fabric_key(module_manager, submodule, fabric_key);
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if (err_code != CMD_EXEC_SUCCESS) {
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return CMD_EXEC_FATAL_ERROR;
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}
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}
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}
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/* Call the XML writer for fabric key */
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err_code = write_xml_fabric_key(fname.c_str(), fabric_key);
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return err_code;
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}
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} /* end namespace openfpga */
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