35 lines
528 B
Verilog
35 lines
528 B
Verilog
/////////////////////////////////////////
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// Functionality: a pipelined 2-input AND
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// where inputs and outputs are registered
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// Author: Xifan Tang
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////////////////////////////////////////
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`timescale 1ns / 1ps
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module and2_pipelined(
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clk,
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a,
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b,
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c);
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input wire clk;
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input wire a;
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input wire b;
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output wire c;
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reg a_reg;
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reg b_reg;
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reg c_reg;
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always @(posedge clk) begin
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a_reg <= a;
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b_reg <= b;
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end
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always @(posedge clk) begin
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c_reg <= a_reg & b_reg;
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end
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assign c = c_reg;
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endmodule
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