180 lines
6.2 KiB
Verilog
180 lines
6.2 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE rev.B2 compliant VGA/LCD Core; Timing Generator ////
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//// Video Timing Generator ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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//// Downloaded from: http://www.opencores.org/projects/vga_lcd ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: vga_vtim.v,v 1.8 2003/05/07 09:48:54 rherveille Exp $
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//
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// $Date: 2003/05/07 09:48:54 $
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// $Revision: 1.8 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: vga_vtim.v,v $
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// Revision 1.8 2003/05/07 09:48:54 rherveille
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// Fixed some Wishbone RevB.3 related bugs.
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// Changed layout of the core. Blocks are located more logically now.
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// Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.
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//
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// Revision 1.7 2003/03/19 12:50:45 rherveille
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// Changed timing generator; made it smaller and easier.
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//
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// Revision 1.6 2002/04/20 10:02:39 rherveille
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// Changed video timing generator.
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// Changed wishbone master vertical gate count code.
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// Fixed a potential bug in the wishbone slave (cursor color register readout).
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//
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// Revision 1.5 2002/01/28 03:47:16 rherveille
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// Changed counter-library.
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// Changed vga-core.
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// Added 32bpp mode.
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//
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//synopsys translate_off
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`include "timescale.v"
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//synopsys translate_on
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module vga_vtim(clk, ena, rst, Tsync, Tgdel, Tgate, Tlen, Sync, Gate, Done);
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// inputs & outputs
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input clk; // master clock
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input ena; // count enable
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input rst; // synchronous active high reset
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input [ 7:0] Tsync; // sync duration
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input [ 7:0] Tgdel; // gate delay
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input [15:0] Tgate; // gate length
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input [15:0] Tlen; // line time / frame time
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output Sync; // synchronization pulse
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output Gate; // gate
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output Done; // done with line/frame
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reg Sync;
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reg Gate;
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reg Done;
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//
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// module body
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//
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// generate timing statemachine
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reg [15:0] cnt, cnt_len;
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wire [16:0] cnt_nxt, cnt_len_nxt;
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wire cnt_done, cnt_len_done;
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assign cnt_nxt = {1'b0, cnt} -17'h1;
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assign cnt_done = cnt_nxt[16];
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assign cnt_len_nxt = {1'b0, cnt_len} -17'h1;
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assign cnt_len_done = cnt_len_nxt[16];
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reg [4:0] state;
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parameter [4:0] idle_state = 5'b00001;
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parameter [4:0] sync_state = 5'b00010;
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parameter [4:0] gdel_state = 5'b00100;
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parameter [4:0] gate_state = 5'b01000;
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parameter [4:0] len_state = 5'b10000;
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always @(posedge clk)
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if (rst)
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begin
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state <= #1 idle_state;
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cnt <= #1 16'h0;
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cnt_len <= #1 16'b0;
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Sync <= #1 1'b0;
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Gate <= #1 1'b0;
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Done <= #1 1'b0;
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end
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else if (ena)
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begin
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cnt <= #1 cnt_nxt[15:0];
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cnt_len <= #1 cnt_len_nxt[15:0];
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Done <= #1 1'b0;
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case (state) // synopsys full_case parallel_case
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idle_state:
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begin
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state <= #1 sync_state;
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cnt <= #1 Tsync;
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cnt_len <= #1 Tlen;
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Sync <= #1 1'b1;
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end
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sync_state:
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if (cnt_done)
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begin
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state <= #1 gdel_state;
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cnt <= #1 Tgdel;
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Sync <= #1 1'b0;
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end
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gdel_state:
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if (cnt_done)
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begin
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state <= #1 gate_state;
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cnt <= #1 Tgate;
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Gate <= #1 1'b1;
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end
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gate_state:
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if (cnt_done)
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begin
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state <= #1 len_state;
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Gate <= #1 1'b0;
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end
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len_state:
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if (cnt_len_done)
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begin
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state <= #1 sync_state;
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cnt <= #1 Tsync;
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cnt_len <= #1 Tlen;
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Sync <= #1 1'b1;
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Done <= #1 1'b1;
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end
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endcase
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end
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endmodule
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