145 lines
5.0 KiB
Verilog
145 lines
5.0 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE rev.B2 compliant VGA/LCD Core; Timing Generator ////
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//// Horizontal and Vertical Timing Generator ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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//// Downloaded from: http://www.opencores.org/projects/vga_lcd ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: vga_tgen.v,v 1.5 2003/05/07 09:48:54 rherveille Exp $
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//
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// $Date: 2003/05/07 09:48:54 $
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// $Revision: 1.5 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: vga_tgen.v,v $
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// Revision 1.5 2003/05/07 09:48:54 rherveille
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// Fixed some Wishbone RevB.3 related bugs.
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// Changed layout of the core. Blocks are located more logically now.
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// Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.
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//
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// Revision 1.4 2002/01/28 03:47:16 rherveille
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// Changed counter-library.
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// Changed vga-core.
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// Added 32bpp mode.
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//
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//synopsys translate_off
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`include "timescale.v"
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//synopsys translate_on
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module vga_tgen(
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clk, clk_ena, rst,
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Thsync, Thgdel, Thgate, Thlen, Tvsync, Tvgdel, Tvgate, Tvlen,
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eol, eof, gate, hsync, vsync, csync, blank
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);
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// inputs & outputs
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input clk;
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input clk_ena;
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input rst;
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// horizontal timing settings inputs
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input [ 7:0] Thsync; // horizontal sync pule width (in pixels)
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input [ 7:0] Thgdel; // horizontal gate delay
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input [15:0] Thgate; // horizontal gate (number of visible pixels per line)
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input [15:0] Thlen; // horizontal length (number of pixels per line)
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// vertical timing settings inputs
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input [ 7:0] Tvsync; // vertical sync pule width (in pixels)
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input [ 7:0] Tvgdel; // vertical gate delay
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input [15:0] Tvgate; // vertical gate (number of visible pixels per line)
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input [15:0] Tvlen; // vertical length (number of pixels per line)
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// outputs
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output eol; // end of line
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output eof; // end of frame
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output gate; // vertical AND horizontal gate (logical AND function)
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output hsync; // horizontal sync pulse
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output vsync; // vertical sync pulse
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output csync; // composite sync
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output blank; // blank signal
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//
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// variable declarations
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//
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wire Hgate, Vgate;
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wire Hdone;
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//
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// module body
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//
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// hookup horizontal timing generator
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vga_vtim hor_gen(
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.clk(clk),
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.ena(clk_ena),
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.rst(rst),
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.Tsync(Thsync),
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.Tgdel(Thgdel),
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.Tgate(Thgate),
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.Tlen(Thlen),
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.Sync(hsync),
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.Gate(Hgate),
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.Done(Hdone)
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);
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// hookup vertical timing generator
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wire vclk_ena = Hdone & clk_ena;
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vga_vtim ver_gen(
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.clk(clk),
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.ena(vclk_ena),
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.rst(rst),
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.Tsync(Tvsync),
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.Tgdel(Tvgdel),
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.Tgate(Tvgate),
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.Tlen(Tvlen),
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.Sync(vsync),
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.Gate(Vgate),
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.Done(eof)
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);
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// assign outputs
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assign eol = Hdone;
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assign gate = Hgate & Vgate;
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assign csync = hsync | vsync;
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assign blank = ~gate;
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endmodule
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