34 lines
1.0 KiB
ReStructuredText
34 lines
1.0 KiB
ReStructuredText
.. _file_format_io_mapping_file:
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I/O Mapping File (.xml)
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-----------------------
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The I/O mapping file aims to show
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- What nets have been mapped to each I/O
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- What is the directionality of each mapped I/O
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An example of design constraints is shown as follows.
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.. code-block:: xml
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<io_mapping>
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<io name="gfpga_pad_GPIO_PAD[6:6]" net="a" dir="input"/>
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<io name="gfpga_pad_GPIO_PAD[1:1]" net="b" dir="input"/>
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<io name="gfpga_pad_GPIO_PAD[9:9]" net="out_c" dir="output"/>
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</io_mapping>
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.. option:: name="<string>"
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The pin name of the FPGA fabric which has been mapped, which should be a valid pin defined in OpenFPGA architecture description.
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.. note:: You should be find the exact pin in the top-level module of FPGA fabric if you output the Verilog netlists.
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.. option:: net="<string>"
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The net name which is actually mapped to a pin, which should be consistent with net definition in your ``.blif`` file.
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.. option:: dir="<string>"
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The direction of an I/O, which can be either ``input`` or ``output``.
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