65 lines
1.2 KiB
Verilog
65 lines
1.2 KiB
Verilog
//-----------------------------------------------------
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// Design Name : testbench for static_dff
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// File Name : ff_tb.v
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// Function : D flip-flop with asyn reset and set
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// Coder : Xifan TANG
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//-----------------------------------------------------
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//----- Time scale: simulation time step and accuracy -----
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`timescale 1ns / 1ps
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module static_dff_tb;
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// voltage sources
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wire set;
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reg reset;
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reg clk;
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reg D;
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wire Q;
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// Parameters
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parameter clk_period = 2; // [ns] a full clock period
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parameter half_clk_period = clk_period / 2; // [ns] a half clock period
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parameter d_period = 2 * clk_period; // [ns] two clock period
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parameter reset_period = 8 * clk_period; // [ns] a full clock period
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// Unit Under Test
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static_dff U0 (set, reset, clk, D, Q);
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// Voltage stimuli
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// Reset : enable in the first clock cycle and then disabled
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initial
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begin
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reset = 1'b1;
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#clk_period reset = ~reset;
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end
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always
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begin
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#reset_period reset = ~reset;
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end
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// set : alway disabled
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assign set = 1'b0;
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// clk: clock generator
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initial
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begin
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clk = 1'b0;
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end
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always
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begin
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#half_clk_period clk = ~clk;
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end
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// D: input, flip every two clock cycles
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initial
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begin
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D = 1'b0;
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end
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always
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begin
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#d_period D = ~D;
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end
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// Q is an output
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//
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endmodule
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