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// SPRAM 4x1 for implementation in LUT4-RAM
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// Asynchronous reading
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module spram_4x1 (
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input clk,
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input[1:0] addr,
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input d_in,
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input wr_en,
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output d_out );
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reg[3:0] mem;
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assign d_out = mem[addr];
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always @(posedge clk) begin
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if(wr_en) begin
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mem[addr] <= d_in;
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end
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end
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endmodule
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