30 lines
680 B
Verilog
30 lines
680 B
Verilog
// ----- Verilog module for buf4 -----
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module buf4(in,
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out);
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//----- INPUT PORTS -----
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input [0:0] in;
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//----- OUTPUT PORTS -----
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output [0:0] out;
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//----- BEGIN wire-connection ports -----
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//----- END wire-connection ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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// ----- Verilog codes of a regular inverter -----
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//assign out = (in === 1'bz)? $random : in;
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assign out = in;
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`ifdef ENABLE_TIMING
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// ------ BEGIN Pin-to-pin Timing constraints -----
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specify
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(in[0] => out[0]) = (0.01, 0.01);
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endspecify
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// ------ END Pin-to-pin Timing constraints -----
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`endif
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endmodule
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// ----- END Verilog module for buf4 -----
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