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adder.v
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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aib.v
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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dff.v
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[HDL] Update dff netlist for SCFF used in configuration chain
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2021-01-04 17:17:35 -07:00 |
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dpram.v
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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dpram1k.v
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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dpram16k.v
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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frac_lut4_arith.v
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[HDL] Add disclaimer for the frac_lut4_arith HDL codes
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2021-02-10 14:50:11 -07:00 |
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frac_mem_32k.v
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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gpio.v
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[HDL] Add new gpio cell with protection circuitry
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2020-11-30 17:52:39 -07:00 |
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latch.v
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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lut6.v
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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mult_32x32.v
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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mult_36x36.v
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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mux2.v
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[HDL] Bug fix in HDL netlist due to port name mismatching
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2021-02-01 11:35:25 -07:00 |
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spram_4x1.v
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Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200)
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2021-01-29 10:19:05 -07:00 |
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sram.v
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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