142 lines
4.2 KiB
C++
142 lines
4.2 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct AttrmvcpPass : public Pass {
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AttrmvcpPass() : Pass("attrmvcp", "move or copy attributes from wires to driving cells") { }
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void help() YS_OVERRIDE
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{
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log("\n");
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log(" attrmvcp [options] [selection]\n");
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log("\n");
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log("Move or copy attributes on wires to the cells driving them.\n");
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log("\n");
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log(" -copy\n");
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log(" By default, attributes are moved. This will only add\n");
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log(" the attribute to the cell, without removing it from\n");
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log(" the wire.\n");
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log("\n");
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log(" -purge\n");
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log(" If no selected cell consumes the attribute, then it is\n");
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log(" left on the wire by default. This option will cause the\n");
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log(" attribute to be removed from the wire, even if no selected\n");
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log(" cell takes it.\n");
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log("\n");
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log(" -driven\n");
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log(" By default, attriburtes are moved to the cell driving the\n");
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log(" wire. With this option set it will be moved to the cell\n");
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log(" driven by the wire instead.\n");
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log("\n");
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log(" -attr <attrname>\n");
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log(" Move or copy this attribute. This option can be used\n");
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log(" multiple times.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing ATTRMVCP pass (move or copy attributes).\n");
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bool copy_mode = false;
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bool driven_mode = false;
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bool purge_mode = false;
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pool<IdString> attrnames;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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std::string arg = args[argidx];
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if (arg == "-copy") {
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copy_mode = true;
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continue;
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}
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if (arg == "-driven") {
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driven_mode = true;
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continue;
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}
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if (arg == "-purge") {
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purge_mode = true;
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continue;
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}
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if (arg == "-attr" && argidx+1 < args.size()) {
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attrnames.insert(RTLIL::escape_id(args[++argidx]));
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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dict<SigBit, pool<Cell*>> net2cells;
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SigMap sigmap(module);
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for (auto cell : module->selected_cells())
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for (auto &conn : cell->connections())
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{
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if (driven_mode) {
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if (cell->input(conn.first))
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for (auto bit : sigmap(conn.second))
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net2cells[bit].insert(cell);
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} else {
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if (cell->output(conn.first))
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for (auto bit : sigmap(conn.second))
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net2cells[bit].insert(cell);
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}
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}
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for (auto wire : module->selected_wires())
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{
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dict<IdString, Const> new_attributes;
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for (auto attr : wire->attributes)
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{
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bool did_something = false;
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if (!attrnames.count(attr.first)) {
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new_attributes[attr.first] = attr.second;
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continue;
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}
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for (auto bit : sigmap(wire))
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if (net2cells.count(bit))
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for (auto cell : net2cells.at(bit)) {
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log("Moving attribute %s=%s from %s.%s to %s.%s.\n", log_id(attr.first), log_const(attr.second),
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log_id(module), log_id(wire), log_id(module), log_id(cell));
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cell->attributes[attr.first] = attr.second;
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did_something = true;
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}
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if (!purge_mode && !did_something)
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new_attributes[attr.first] = attr.second;
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}
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if (!copy_mode)
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wire->attributes.swap(new_attributes);
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}
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}
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}
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} AttrmvcpPass;
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PRIVATE_NAMESPACE_END
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