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OpenFPGA/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config
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tangxifan 0d82e4939c [Test] Use unified quicklogic synthesis script and enable end-of-flow tests 2021-02-26 09:35:40 -07:00
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bitstream_annotation.xml [Test] Add LUT adder test using quicklogic synthesis script 2021-02-23 16:50:58 -07:00
task.conf [Test] Use unified quicklogic synthesis script and enable end-of-flow tests 2021-02-26 09:35:40 -07:00