OpenFPGA/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config
Lalit Sharma 0cbad747a1 Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family 2021-03-04 01:10:47 -08:00
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pin_constraints.xml [Test] Bug fix in the 5clock test case 2021-02-22 11:46:23 -07:00
repack_pin_constraints.xml [Test] Bug fix in the 5clock test case 2021-02-22 11:46:23 -07:00
task.conf Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family 2021-03-04 01:10:47 -08:00