tangxifan 7b4f06ed7d [test] validate mux2 at last stage		2024-09-18 17:40:13 -07:00
..
spice	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
spice_testbench	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
verilog	[test] validate mux2 at last stage	2024-09-18 17:40:13 -07:00
verilog_testbench	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
Makefile	[test] add regression test to validate compilation of openfpga cell library files	2022-05-09 16:00:51 +08:00
verilog_sources.f	[test] add regression test to validate compilation of openfpga cell library files	2022-05-09 16:00:51 +08:00