tangxifan 28904ff526 [Engine] Bug fix on wrong port type for shift register chains		2021-10-03 12:31:58 -07:00
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annotation	[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes	2021-04-24 14:53:29 -06:00
base	[Engine] Upgrade check codes for WL CCFF	2021-10-01 17:23:10 -07:00
fabric	[Engine] Bug fix on wrong port type for shift register chains	2021-10-03 12:31:58 -07:00
fpga_bitstream	[FPGA-Bitstream] Enable fast configuration for QuickLogic memory banks	2021-10-01 16:23:38 -07:00
fpga_sdc	[Engine] Support programming shift register clock in XML syntax	2021-10-01 11:00:38 -07:00
fpga_spice	[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming	2020-12-05 12:44:09 -07:00
fpga_verilog	[FPGA-Verilog] Bug fix in estimating the simulation period for QuickLogic memory bank using BL/WL shift registers	2021-10-03 12:11:20 -07:00
mux_lib	[Engine] Support WLR port in OpenFPGA architecture file and fabric generator	2021-09-20 16:05:36 -07:00
repack	[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes	2021-04-24 14:53:29 -06:00
tile_direct	bug fixed in tile direct builder	2020-03-21 12:43:56 -06:00
utils	[FPGA-Verilog] Many bug fixes	2021-10-02 23:39:53 -07:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	[Tool] Add --version to openfpga shell option and a command to openfpga shell	2021-01-27 16:03:46 -07:00