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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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27f4a174b0
OpenFPGA
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openfpga_flow
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tasks
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fpga_verilog
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adder
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tangxifan
8853370c60
[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file
2021-02-04 20:20:10 -07:00
..
hard_adder
/config
[Test] Add adder test cases
2021-02-01 10:42:24 -07:00
soft_adder
/config
[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file
2021-02-04 20:20:10 -07:00