29 lines
1.4 KiB
XML
29 lines
1.4 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<!--
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XML file specification is primarily to define the mapping of the interface cell ports defined
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in vpr_arch xml, to the EFPGA IO interface port names. This mapping is required by OpenFPGA
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alongwith architecture definition file i.e. vpr_arch xml file. OpenFPGA will process this
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file and use this information for IO placement and then later on use this to map it with the
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user-defined pin-mapping file.
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-->
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<DEVICE name= "k4_N4_tileable_40nm" family="k4n4" width="6" height="6" z="8">
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<IO>
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<TOP_IO y="5">
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<CELL port_name="output" mapped_name="gfpga_pad_IO_F2A[0:31]" startx="1" endx="4"/>
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<CELL port_name="input" mapped_name="gfpga_pad_IO_A2F[0:31]" startx="1" endx="4"/>
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</TOP_IO>
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<RIGHT_IO x="5">
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<CELL port_name="output" mapped_name="gfpga_pad_IO_F2A[32:63]" starty="4" endy="1"/>
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<CELL port_name="input" mapped_name="gfpga_pad_IO_A2F[32:63]" starty="4" endy="1"/>
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</RIGHT_IO>
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<BOTTOM_IO y="0">
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<CELL port_name="output" mapped_name="gfpga_pad_IO_F2A[64:95]" startx="4" endx="1"/>
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<CELL port_name="input" mapped_name="gfpga_pad_IO_A2F[64:95]" startx="4" endx="1"/>
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</BOTTOM_IO>
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<LEFT_IO x="0">
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<CELL port_name="output" mapped_name="gfpga_pad_IO_F2A[96:127]" starty="1" endy="4"/>
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<CELL port_name="input" mapped_name="gfpga_pad_IO_A2F[96:127]" starty="1" endy="4"/>
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</LEFT_IO>
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</IO>
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</DEVICE>
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