riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
OpenFPGA/vpr7_x2p/vpr/SRC/fpga_x2p
History
tangxifan 27b996337a fixed a critical bug in Compact Verilog generation for SB/CBs 2019-05-24 16:14:46 -06:00
..
base updated bitstream to use new RRSwitchBlock as well as the report timing engine 2019-05-24 12:54:10 -06:00
bitstream updated bitstream to use new RRSwitchBlock as well as the report timing engine 2019-05-24 12:54:10 -06:00
clb_pin_remap cleaned unused variables 2019-05-13 14:45:02 -06:00
router cleaned unused variables 2019-05-13 14:45:02 -06:00
shell Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-13 14:45:57 -06:00
spice Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-13 14:45:57 -06:00
verilog fixed a critical bug in Compact Verilog generation for SB/CBs 2019-05-24 16:14:46 -06:00