tangxifan 27153bbc89 [FPGA-Verilog] Bug fix in matching shift register clocks between verilog ports and simulation setting definition		2021-10-06 13:38:51 -07:00
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src	[FPGA-Verilog] Bug fix in matching shift register clocks between verilog ports and simulation setting definition	2021-10-06 13:38:51 -07:00
CMakeLists.txt	[Tool] Deploy pin constraints to preconfig Verilog module generation	2021-01-19 16:56:30 -07:00