tangxifan 2692d0fc35 adding XML parsing for SPICE and Verilog netlist for each circuit model		2020-01-14 08:45:27 -07:00
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arch	reorganized the read XML openfpga arch	2020-01-14 08:33:48 -07:00
src	adding XML parsing for SPICE and Verilog netlist for each circuit model	2020-01-14 08:45:27 -07:00
test	reorganized the read XML openfpga arch	2020-01-14 08:33:48 -07:00
CMakeLists.txt	initial commit on parser for reading openfpga arch xml	2020-01-12 21:33:28 -07:00