riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
OpenFPGA/openfpga_flow/openfpga_cell_library
History
AurelienAlacchi 3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200) 
* Add required files for LUTRAM integration and testing

* Add task for lutram

* Repair format (tab and space mismatched)

* Add disclaimer in architecture file

Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
 		2021-01-29 10:19:05 -07:00
..
spice [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
spice_testbench [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
verilog Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200) 2021-01-29 10:19:05 -07:00
verilog_testbench [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00