tangxifan 23795d6474 [Test] Update golden netlists		2022-01-25 20:37:08 -08:00
..
custom_fabric_netlist_location/config	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
explicit_multi_verilog_files/config	Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.	2022-01-21 02:21:00 +05:00
fabric_key	[Test] Bug fix in test cases	2021-10-11 10:28:09 -07:00
fixed_device_support/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
fixed_simulation_settings	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
full_testbench	[Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp	2022-01-25 16:41:36 -08:00
generate_fabric	[Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification	2021-04-11 17:26:27 -06:00
generate_testbench/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
global_tile_ports	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
k4_series	Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.	2022-01-21 02:21:00 +05:00
no_time_stamp	[Test] Update golden netlists	2022-01-25 20:37:08 -08:00
preconfig_testbench	[Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp	2022-01-25 16:41:36 -08:00
tile_organization	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
verific_test/config	Added 'basic_tests/verific_test' test-case.	2021-11-01 18:20:57 +05:00
yosys_only/config	Test case for yosys-only flow added	2022-01-14 15:37:47 +05:00