115 lines
5.2 KiB
ReStructuredText
115 lines
5.2 KiB
ReStructuredText
Link circuit modules
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--------------------
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Each defined SPICE model should be linked to a FPGA module defined in the original part of architecture descriptions. It helps FPGA-SPICE creating the SPICE netlists for logic/routing blocks. Since the original part lacks such support, we create a few XML properties to link to SPICE models.
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SRAM
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====
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To link the defined SPICE model of SRAM into the FPGA architecture description, a new line in XML format should be added under the XML node device. The new XML node is named as sram, which defines the area of a SRAM and the name of SPICE model to be linked. And example is shown as follows:
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.. code-block:: xml
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<sram area=”int” spice_model_name=”string”>
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<sram>
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<spice organization="string" spice_model_name="scff"/>
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<verilog organization="string" spice_model_name="scff"/>
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</sram>
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* area is expressed in terms of the number of minimum width transistors. The SRAM area defined in this line is used in the area estimation of global routing multiplexers. spice_model_name should match the name of SPICE model that have been defined under XML node module_spice_model. The type of the linked SPICE model should be sram.
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* organization: the type of configuration circuits. available options: [scan-chain|memory_bank|standalone]. :numref:`fig_sram` illustrates an exmample where a memory organiation using memory decoders and 6-transistor SRAMs.
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.. _fig_sram:
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.. figure:: figures/sram.png
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:scale: 100%
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:alt: map to buried treasure
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Example of a memory organization using memory decoders
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.. note:: Currently SPICE only supports standalone memory organization.
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.. note:: Currently RRAM-based FPGA only supports memory-bank organization for Verilog Generator.
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Here is an example.
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.. code-block:: xml
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<sram area=”4” spice_model_name=”sram6T”>
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Switch Blocks
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=============
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Original VPR architecture description contains a XML node called switchlist under which all the multiplexers of switch blocks are described.
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To link a defined SPICE model to a multiplexer in the switch blocks, a new XML property spice_model_name should added to the descriptions.
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Here is an example:
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.. code-block:: xml
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<switchlist>
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<switch type=”mux” name=”string” R=”float” Cin=”float” Cout=”float” Tdel=”float” mux_trans_size=”float” buf_size=”float” spice_model_name=”string”/>
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</switchlist>
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* spice_model_name: should match a SPICE model whose type is mux defined under module_spice_models.
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Connection Boxes
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================
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To link the defined SPICE model of multiplexer to the Connection Boxes, a spice_model_name should be added to the definition of Connection Boxes switches. However, the original architecture descriptions do not offer a switch description for connection boxes as they do for the switch blocks.
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Therefore, FPGA-SPICE requires a new XML node called cblock under the root XML node architecture, where a switch for connection boxes can be defined.
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Here is the example:
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.. code-block:: xml
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<cblock>
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<switch type=”mux” name=”string” R=”float” Cin=”float” Cout=”float” Tdel=”float” mux_trans_size=”float” buf_size=”float” spice_model_name=”string”/>
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</cblock>
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* spice_model_name: should match a SPICE model whose type is mux defined under module_spice_models.
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Channel Wire Segments
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=====================
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Simliar to the SB and CB, the channel wire segments in the original architecture descriptions can be adapted to provide a link to the defined SPICE model.
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.. code-block:: xml
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<segmentlist>
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<segment freq=”float” length=”int” type=”string” Rmetal=”float” Cmetal=”float” spice_model_name=”string”/>
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</segmentlist>
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* spice_model_name: should match a SPICE model whose type is chan_wire defined under module_spice_models.
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Primitive Blocks inside Configurable Logic Blocks
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=================================================
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The architecture description employs a hierarchy of pb_types to depicting the sub modules and complex interconnections inside logic blocks. Each leaf node and interconnection in pb_type hierarchy should be linked to a SPICE model.
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.. code-block:: xml
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<pb_type name="clb" idle_mode_name="ble" physical_mode_name="ble">
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<pb_type name="ble">
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<pb_type name="lut" spice_model_name="lut6">
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<pb_type name="ff" spice_model_name="dff">
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<interconnect>
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<mux input="lut.out ff.Q" output="ble.out" spice_model_name="mux_1level">
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</interconnect>
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</pb_type>
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<interconnect>
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<mux input="ble.out clb.in" output="ble.in" spice_model_name="mux_2level">
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</interconnect>
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</pb_type>
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* spice_model_name: should match a SPICE model defined under module_spice_models. For the interconnection type direct, the type of the linked SPICE model should be wire. For mux, the type of the linked SPICE model should be mux. For complete, the type of the linked SPICE model can be either mux or wire, depending on the case.
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* idle_mode_name: tell the name of the mode that the pb_type is configured to be by default. This is critical in building SPICE netlists for unused logic blocks.
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* physical_mode_name: tell the name of the mode that describes the physical implementation of the block. This is critical in modeling actual circuit designs and architecture of a FPGA.
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