riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
OpenFPGA/yosys/examples/gowin/demo.sdc

2 lines
69 B
Tcl
Raw Blame History

create_clock -name clk -period 20 -waveform {0 10} [get_ports {clk}]
Reference in New Issue View Git Blame Copy Permalink