riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
OpenFPGA/yosys/manual/CHAPTER_Eval/or1200_ys.prj

2 lines
27 B
Plaintext
Raw Blame History

verilog work "or1200_ys.v"
Reference in New Issue View Git Blame Copy Permalink