100 lines
2.2 KiB
Verilog
100 lines
2.2 KiB
Verilog
//------ Module: sram6T_blwl -----//
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//------ Verilog file: sram.v -----//
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//------ Author: Xifan TANG -----//
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module sram6T_blwl(
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//input read,
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//input nequalize,
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input din, // Data input
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output dout, // Data output
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output doutb, // Data output
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input bl, // Bit line control signal
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input wl, // Word line control signal
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input blb // Inverted Bit line control signal
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);
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//----- local variable need to be registered
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reg a;
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//----- when wl is enabled, we can read in data from bl
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always @(bl, wl)
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begin
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//----- Cases to program internal memory bit
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//----- case 1: bl = 1, wl = 1, a -> 0
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if ((1'b1 == bl)&&(1'b1 == wl)) begin
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a <= 1'b1;
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end
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//----- case 2: bl = 0, wl = 1, a -> 0
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if ((1'b0 == bl)&&(1'b1 == wl)) begin
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a <= 1'b0;
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end
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end
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`ifdef INITIALIZATION
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initial begin
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$signal_force("a", "0", 0, 1, , 1);
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end
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`endif
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// dout is short-wired to din
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assign dout = a;
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//---- doutb is always opposite to dout
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assign doutb = ~dout;
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endmodule
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module sram6T_rram(
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input read,
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input nequalize,
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input din, // Data input
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output dout, // Data output
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output doutb, // Data output
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// !!! Port bit position should start from LSB to MSB
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// Follow this convention for BL/WLs in each module!
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input [0:2] bl, // Bit line control signal
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input [0:2] wl// Word line control signal
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);
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//----- local variable need to be registered
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//----- Modeling two RRAMs
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reg r0, r1;
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always @(bl[0], wl[2])
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begin
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//----- Cases to program r0
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//----- case 1: bl[0] = 1, wl[2] = 1, r0 -> 0
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if ((1'b1 == bl[0])&&(1'b1 == wl[2])) begin
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r0 <= 0;
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end
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end
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always @(bl[2], wl[0])
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begin
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//----- case 2: bl[2] = 1, wl[0] = 1, r0 -> 1
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if ((1'b1 == bl[2])&&(1'b1 == wl[0])) begin
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r0 <= 1;
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end
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end
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always @(bl[1], wl[2])
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begin
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//----- Cases to program r1
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//----- case 1: bl[1] = 1, wl[2] = 1, r0 -> 0
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if ((1'b1 == bl[1])&&(1'b1 == wl[2])) begin
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r1 <= 0;
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end
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end
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always @( bl[2], wl[1])
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begin
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//----- case 2: bl[2] = 1, wl[1] = 1, r0 -> 1
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if ((1'b1 == bl[2])&&(1'b1 == wl[1])) begin
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r1 <= 1;
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end
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end
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// dout is r0 AND r1
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assign dout = r0 | (~r1);
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//---- doutb is always opposite to dout
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assign doutb = ~dout;
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endmodule
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