119 lines
1.8 KiB
Verilog
119 lines
1.8 KiB
Verilog
module Controller(
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output reg [11:0] control_signals,
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input [3:0] opcode,
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input clk,
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input clr_
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);
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reg [3:0] ps, ns;
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always @(posedge clk)
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begin
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if(~clr_) ps <= 4'd0;
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else ps <= ns;
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end
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always @(*)
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begin
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case(ps)
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0:
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begin
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control_signals = 12'h3e3;
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ns = 4'd1;
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end
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1: //T1
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begin
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control_signals = 12'h5e3;
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ns = 4'd2;
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end
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2: //T2
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begin
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// control_signals = 12'hbe3;
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control_signals = 12'h863;
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ns = 4'd3;
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end
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3: //T3
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begin
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// control_signals = 12'h263;
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control_signals = 12'h3e3;
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if(opcode == 4'd0) //LDA
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ns = 4'd4;
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else if(opcode == 4'd1) //ADD
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ns = 4'd6;
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else if(opcode == 4'd2) //SUB
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ns = 4'd9;
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else if(opcode == 4'd14) //OUT
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ns = 4'd12;
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else if(opcode == 4'd15) //HLT
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ns = 4'd13;
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end
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4: //LDA
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begin
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control_signals = 12'h1a3;
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ns = 4'd5;
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end
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5: //LDA
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begin
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control_signals = 12'h2c3;
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ns = 4'd1;
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end
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6: //ADD
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begin
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control_signals = 12'h1a3;
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ns = 4'd7;
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end
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7: //ADD
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begin
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control_signals = 12'h2e1;
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ns = 4'd8;
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end
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8: //ADD
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begin
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control_signals = 12'h3c7;
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ns = 4'd1;
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end
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9: //SUB
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begin
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control_signals = 12'h1a3;
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ns = 4'd10;
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end
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10: //SUB
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begin
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control_signals = 12'h2e1;
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ns = 4'd11;
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end
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11: //SUB
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begin
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control_signals = 12'h3cf;
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ns = 4'd1;
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end
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12: //OUT
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begin
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control_signals = 12'h3f2;
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ns = 4'd1;
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end
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13: //HLT
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ns = 4'd13;
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default:
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begin
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ns = 4'd0;
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control_signals = 12'h3e3;
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end
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endcase
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end
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endmodule |