185 lines
5.4 KiB
Verilog
185 lines
5.4 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// USB 1.1 PHY ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/usb_phy/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: usb_phy.v,v 1.4 2003/10/21 05:58:40 rudi Exp $
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//
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// $Date: 2003/10/21 05:58:40 $
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// $Revision: 1.4 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: usb_phy.v,v $
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// Revision 1.4 2003/10/21 05:58:40 rudi
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// usb_rst is no longer or'ed with the incomming reset internally.
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// Now usb_rst is simply an output, the application can decide how
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// to utilize it.
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//
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// Revision 1.3 2003/10/19 17:40:13 rudi
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// - Made core more robust against line noise
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// - Added Error Checking and Reporting
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// (See README.txt for more info)
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//
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// Revision 1.2 2002/09/16 16:06:37 rudi
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// Changed top level name to be consistent ...
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//
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// Revision 1.1.1.1 2002/09/16 14:26:59 rudi
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// Created Directory Structure
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//
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//
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//
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//
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//
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//
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//
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//
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`include "timescale.v"
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module usb_phy(clk, rst, phy_tx_mode, usb_rst,
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// Transciever Interface
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txdp, txdn, txoe,
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rxd, rxdp, rxdn,
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// UTMI Interface
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DataOut_i, TxValid_i, TxReady_o, RxValid_o,
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RxActive_o, RxError_o, DataIn_o, LineState_o
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);
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input clk;
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input rst;
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input phy_tx_mode;
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output usb_rst;
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output txdp, txdn, txoe;
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input rxd, rxdp, rxdn;
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input [7:0] DataOut_i;
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input TxValid_i;
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output TxReady_o;
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output [7:0] DataIn_o;
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output RxValid_o;
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output RxActive_o;
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output RxError_o;
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output [1:0] LineState_o;
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///////////////////////////////////////////////////////////////////
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//
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// Local Wires and Registers
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//
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reg [4:0] rst_cnt;
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reg usb_rst;
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wire fs_ce;
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wire rst;
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///////////////////////////////////////////////////////////////////
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//
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// Misc Logic
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//
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///////////////////////////////////////////////////////////////////
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//
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// TX Phy
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//
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usb_tx_phy i_tx_phy(
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.clk( clk ),
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.rst( rst ),
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.fs_ce( fs_ce ),
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.phy_mode( phy_tx_mode ),
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// Transciever Interface
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.txdp( txdp ),
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.txdn( txdn ),
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.txoe( txoe ),
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// UTMI Interface
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.DataOut_i( DataOut_i ),
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.TxValid_i( TxValid_i ),
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.TxReady_o( TxReady_o )
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);
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///////////////////////////////////////////////////////////////////
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//
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// RX Phy and DPLL
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//
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usb_rx_phy i_rx_phy(
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.clk( clk ),
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.rst( rst ),
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.fs_ce( fs_ce ),
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// Transciever Interface
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.rxd( rxd ),
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.rxdp( rxdp ),
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.rxdn( rxdn ),
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// UTMI Interface
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.DataIn_o( DataIn_o ),
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.RxValid_o( RxValid_o ),
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.RxActive_o( RxActive_o ),
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.RxError_o( RxError_o ),
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.RxEn_i( txoe ),
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.LineState( LineState_o )
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);
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///////////////////////////////////////////////////////////////////
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//
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// Generate an USB Reset is we see SE0 for at least 2.5uS
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//
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`ifdef USB_ASYNC_REST
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always @(posedge clk or negedge rst)
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`else
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always @(posedge clk)
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`endif
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if(!rst) rst_cnt <= 5'h0;
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else
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if(LineState_o != 2'h0) rst_cnt <= 5'h0;
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else
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if(!usb_rst && fs_ce) rst_cnt <= rst_cnt + 5'h1;
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always @(posedge clk)
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usb_rst <= (rst_cnt == 5'h1f);
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endmodule
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