211 lines
6.5 KiB
Verilog
211 lines
6.5 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE Memory Controller ////
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//// Refresh Module ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: mc_refresh.v,v 1.4 2002/01/21 13:08:52 rudi Exp $
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//
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// $Date: 2002/01/21 13:08:52 $
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// $Revision: 1.4 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: mc_refresh.v,v $
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// Revision 1.4 2002/01/21 13:08:52 rudi
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//
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// Fixed several minor bugs, cleaned up the code further ...
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//
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// Revision 1.3 2001/12/11 02:47:19 rudi
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//
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// - Made some changes not to expect clock during reset ...
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//
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// Revision 1.2 2001/09/24 00:38:21 rudi
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//
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// Changed Reset to be active high and async.
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//
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// Revision 1.1 2001/07/29 07:34:41 rudi
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//
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//
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// 1) Changed Directory Structure
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// 2) Fixed several minor bugs
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//
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// Revision 1.3 2001/06/12 15:19:49 rudi
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//
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//
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// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
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//
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// Revision 1.2 2001/06/03 11:37:17 rudi
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//
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//
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// 1) Fixed Chip Select Mask Register
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// - Power On Value is now all ones
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// - Comparison Logic is now correct
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//
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// 2) All resets are now asynchronous
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//
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// 3) Converted Power On Delay to an configurable item
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//
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// 4) Added reset to Chip Select Output Registers
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//
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// 5) Forcing all outputs to Hi-Z state during reset
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//
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// Revision 1.1.1.1 2001/05/13 09:39:47 rudi
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// Created Directory Structure
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//
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//
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//
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//
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`include "mc_defines.v"
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module mc_refresh(clk, rst,
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cs_need_rfr, ref_int, rfr_req, rfr_ack,
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rfr_ps_val
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);
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input clk, rst;
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input [7:0] cs_need_rfr;
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input [2:0] ref_int;
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output rfr_req;
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input rfr_ack;
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input [7:0] rfr_ps_val;
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////////////////////////////////////////////////////////////////////
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//
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// Local Registers & Wires
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//
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reg rfr_en;
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reg [7:0] ps_cnt;
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wire ps_cnt_clr;
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reg rfr_ce;
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reg [7:0] rfr_cnt;
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reg rfr_clr;
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reg rfr_req;
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reg rfr_early;
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/*
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Refresh generation
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The prescaler generates a 0.48828 uS clock enable
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The refresh counter generates the following refresh rates:
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(Actual values are about 0.63% below the desired values).
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This is for a 200 Mhz WISHBONE Bus.
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0.970 uS,
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1.940
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3.880
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7.760
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15.520
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32.040
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62.080
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124.160 uS
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(desired values)
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0.976 uS
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1.953
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3.906
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7.812
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15.625
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31.250
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62.500
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125.000 uS
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*/
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////////////////////////////////////////////////////////////////////
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//
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// Prescaler
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//
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always @(posedge clk or posedge rst)
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if(rst) rfr_en <= #1 1'b0;
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else rfr_en <= #1 |cs_need_rfr;
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always @(posedge clk or posedge rst)
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if(rst) ps_cnt <= #1 8'h0;
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else
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if(ps_cnt_clr) ps_cnt <= #1 8'h0;
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else
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if(rfr_en) ps_cnt <= #1 ps_cnt + 8'h1;
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assign ps_cnt_clr = (ps_cnt == rfr_ps_val) & (rfr_ps_val != 8'h0);
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always @(posedge clk or posedge rst)
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if(rst) rfr_early <= #1 1'b0;
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else rfr_early <= #1 (ps_cnt == rfr_ps_val);
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////////////////////////////////////////////////////////////////////
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//
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// Refresh Counter
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//
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always @(posedge clk or posedge rst)
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if(rst) rfr_ce <= #1 1'b0;
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else rfr_ce <= #1 ps_cnt_clr;
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always @(posedge clk or posedge rst)
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if(rst) rfr_cnt <= #1 8'h0;
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else
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if(rfr_ack) rfr_cnt <= #1 8'h0;
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else
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if(rfr_ce) rfr_cnt <= #1 rfr_cnt + 8'h1;
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always @(posedge clk)
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case(ref_int) // synopsys full_case parallel_case
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3'h0: rfr_clr <= #1 rfr_cnt[0] & rfr_early;
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3'h1: rfr_clr <= #1 &rfr_cnt[1:0] & rfr_early;
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3'h2: rfr_clr <= #1 &rfr_cnt[2:0] & rfr_early;
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3'h3: rfr_clr <= #1 &rfr_cnt[3:0] & rfr_early;
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3'h4: rfr_clr <= #1 &rfr_cnt[4:0] & rfr_early;
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3'h5: rfr_clr <= #1 &rfr_cnt[5:0] & rfr_early;
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3'h6: rfr_clr <= #1 &rfr_cnt[6:0] & rfr_early;
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3'h7: rfr_clr <= #1 &rfr_cnt[7:0] & rfr_early;
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endcase
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always @(posedge clk or posedge rst)
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if(rst) rfr_req <= #1 1'b0;
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else
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if(rfr_ack) rfr_req <= #1 1'b0;
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else
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if(rfr_clr) rfr_req <= #1 1'b1;
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endmodule
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