237 lines
7.8 KiB
Verilog
237 lines
7.8 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE Memory Controller ////
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//// Open Bank & Row Tracking Block ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: mc_obct.v,v 1.4 2002/01/21 13:08:52 rudi Exp $
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//
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// $Date: 2002/01/21 13:08:52 $
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// $Revision: 1.4 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: mc_obct.v,v $
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// Revision 1.4 2002/01/21 13:08:52 rudi
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//
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// Fixed several minor bugs, cleaned up the code further ...
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//
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// Revision 1.3 2001/11/29 02:16:28 rudi
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//
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//
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// - More Synthesis cleanup, mostly for speed
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// - Several bug fixes
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// - Changed code to avoid auto-precharge and
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// burst-terminate combinations (apparently illegal ?)
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// Now we will do a manual precharge ...
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//
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// Revision 1.2 2001/09/24 00:38:21 rudi
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//
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// Changed Reset to be active high and async.
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//
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// Revision 1.1 2001/07/29 07:34:41 rudi
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//
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//
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// 1) Changed Directory Structure
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// 2) Fixed several minor bugs
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//
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// Revision 1.3 2001/06/12 15:19:49 rudi
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//
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//
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// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
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//
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// Revision 1.2 2001/06/03 11:37:17 rudi
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//
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//
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// 1) Fixed Chip Select Mask Register
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// - Power On Value is now all ones
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// - Comparison Logic is now correct
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//
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// 2) All resets are now asynchronous
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//
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// 3) Converted Power On Delay to an configurable item
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//
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// 4) Added reset to Chip Select Output Registers
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//
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// 5) Forcing all outputs to Hi-Z state during reset
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//
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// Revision 1.1.1.1 2001/05/13 09:39:45 rudi
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// Created Directory Structure
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//
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//
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//
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//
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`include "mc_defines.v"
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module mc_obct(clk, rst, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all,
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bank_open, any_bank_open, row_same);
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input clk, rst;
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input [12:0] row_adr;
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input [1:0] bank_adr;
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input bank_set;
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input bank_clr;
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input bank_clr_all;
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output bank_open;
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output any_bank_open;
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output row_same;
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////////////////////////////////////////////////////////////////////
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//
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// Local Registers & Wires
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//
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reg bank0_open, bank1_open, bank2_open, bank3_open;
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reg bank_open;
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reg [12:0] b0_last_row;
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reg [12:0] b1_last_row;
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reg [12:0] b2_last_row;
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reg [12:0] b3_last_row;
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wire row0_same, row1_same, row2_same, row3_same;
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reg row_same;
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////////////////////////////////////////////////////////////////////
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//
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// Bank Open/Closed Tracking
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//
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always @(posedge clk or posedge rst)
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if(rst) bank0_open <= #1 1'b0;
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else
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if((bank_adr == 2'h0) & bank_set) bank0_open <= #1 1'b1;
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else
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if((bank_adr == 2'h0) & bank_clr) bank0_open <= #1 1'b0;
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else
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if(bank_clr_all) bank0_open <= #1 1'b0;
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always @(posedge clk or posedge rst)
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if(rst) bank1_open <= #1 1'b0;
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else
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if((bank_adr == 2'h1) & bank_set) bank1_open <= #1 1'b1;
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else
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if((bank_adr == 2'h1) & bank_clr) bank1_open <= #1 1'b0;
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else
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if(bank_clr_all) bank1_open <= #1 1'b0;
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always @(posedge clk or posedge rst)
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if(rst) bank2_open <= #1 1'b0;
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else
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if((bank_adr == 2'h2) & bank_set) bank2_open <= #1 1'b1;
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else
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if((bank_adr == 2'h2) & bank_clr) bank2_open <= #1 1'b0;
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else
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if(bank_clr_all) bank2_open <= #1 1'b0;
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always @(posedge clk or posedge rst)
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if(rst) bank3_open <= #1 1'b0;
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else
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if((bank_adr == 2'h3) & bank_set) bank3_open <= #1 1'b1;
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else
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if((bank_adr == 2'h3) & bank_clr) bank3_open <= #1 1'b0;
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else
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if(bank_clr_all) bank3_open <= #1 1'b0;
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always @(bank_adr or bank0_open or bank1_open or bank2_open or bank3_open)
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case(bank_adr) // synopsys full_case parallel_case
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2'h0: bank_open = bank0_open;
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2'h1: bank_open = bank1_open;
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2'h2: bank_open = bank2_open;
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2'h3: bank_open = bank3_open;
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endcase
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assign any_bank_open = bank0_open | bank1_open | bank2_open | bank3_open;
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////////////////////////////////////////////////////////////////////
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//
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// Raw Address Tracking
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//
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always @(posedge clk)
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if((bank_adr == 2'h0) & bank_set) b0_last_row <= #1 row_adr;
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always @(posedge clk)
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if((bank_adr == 2'h1) & bank_set) b1_last_row <= #1 row_adr;
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always @(posedge clk)
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if((bank_adr == 2'h2) & bank_set) b2_last_row <= #1 row_adr;
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always @(posedge clk)
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if((bank_adr == 2'h3) & bank_set) b3_last_row <= #1 row_adr;
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////////////////////////////////////////////////////////////////////
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//
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// Raw address checking
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//
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assign row0_same = (b0_last_row == row_adr);
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assign row1_same = (b1_last_row == row_adr);
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assign row2_same = (b2_last_row == row_adr);
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assign row3_same = (b3_last_row == row_adr);
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always @(bank_adr or row0_same or row1_same or row2_same or row3_same)
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case(bank_adr) // synopsys full_case parallel_case
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2'h0: row_same = row0_same;
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2'h1: row_same = row1_same;
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2'h2: row_same = row2_same;
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2'h3: row_same = row3_same;
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endcase
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endmodule
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// This is used for unused Chip Selects
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module mc_obct_dummy(clk, rst, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all,
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bank_open, any_bank_open, row_same);
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input clk, rst;
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input [12:0] row_adr;
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input [1:0] bank_adr;
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input bank_set;
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input bank_clr;
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input bank_clr_all;
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output bank_open;
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output any_bank_open;
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output row_same;
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assign bank_open = 1'b0;
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assign any_bank_open = 1'b0;
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assign row_same = 1'b0;
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endmodule
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