80 lines
3.2 KiB
Verilog
80 lines
3.2 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// Tripple DES ////
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//// Tripple DES Top Level module ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002 Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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module des3(desOut, desIn, key1, key2, key3, decrypt, clk);
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output [63:0] desOut;
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input [63:0] desIn;
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input [55:0] key1;
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input [55:0] key2;
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input [55:0] key3;
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input decrypt;
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input clk;
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wire [55:0] key_a;
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wire [55:0] key_b;
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wire [55:0] key_c;
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wire [63:0] stage1_out, stage2_out;
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reg [55:0] key_b_r [16:0];
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reg [55:0] key_c_r [33:0];
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integer i;
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assign key_a = decrypt ? key3 : key1;
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assign key_b = key2;
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assign key_c = decrypt ? key1 : key3;
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always @(posedge clk)
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key_b_r[0] <= #1 key_b;
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always @(posedge clk)
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for(i=0;i<16;i=i+1)
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key_b_r[i+1] <= #1 key_b_r[i];
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always @(posedge clk)
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key_c_r[0] <= #1 key_c;
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always @(posedge clk)
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for(i=0;i<33;i=i+1)
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key_c_r[i+1] <= #1 key_c_r[i];
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des u0( .desOut(stage1_out), .desIn(desIn), .key(key_a), .decrypt(decrypt), .clk(clk) );
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des u1( .desOut(stage2_out), .desIn(stage1_out), .key(key_b_r[16]), .decrypt(!decrypt), .clk(clk) );
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des u2( .desOut(desOut), .desIn(stage2_out), .key(key_c_r[33]), .decrypt(decrypt), .clk(clk) );
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endmodule
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